S
Scott E. Thompson
Researcher at Fujitsu
Publications - 132
Citations - 8470
Scott E. Thompson is an academic researcher from Fujitsu. The author has contributed to research in topics: Transistor & CMOS. The author has an hindex of 38, co-authored 132 publications receiving 8077 citations. Previous affiliations of Scott E. Thompson include Intel & University of Florida.
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Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Journal ArticleDOI
Moore's law: the future of Si microelectronics
TL;DR: In this article, the authors describe the history of the microelectronics industry and its explosive growth driven by two factors: Noyce and Kilby inventing the planar integrated circuit (PIC) and the advantageous characteristics that result from scaling (shrinking) solid-state devices.
Journal ArticleDOI
Uniaxial-process-induced strained-Si: extending the CMOS roadmap
TL;DR: In this article, a more complete data set of n-and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement.
Journal ArticleDOI
A logic nanotechnology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,S. Cea,R. Chau,G. Glass,T. Hoffman,Jason Klaus,Z. Ma,B. McIntyre,Anand Portland Murthy,B. Obradovic,Lucian Shifren,Swaminathan Sivakumar,S. Tyagi,Tahir Ghani,Kaizad Mistry,Mark T. Bohr,Y. El-Mansy +18 more
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.