Fast and accurate thermal analysis is crucial for determining the propagation of heat and tracking the formation of hotspots in integrated circuits (ICs). Existing academic thermal analysis tools primarily use compact models to accelerate thermal simulations but are limited to linear problems on relatively simple circuit geometries. The Manchester Thermal Analyzer (MTA) is a comprehensive tool that allows for fast and highly accurate linear and nonlinear thermal simulations of complex physical structures including the IC, the package, and the heatsink. The MTA is targeted for 2.5/3-D IC designs but also handles standard planar ICs. The MTA discretizes the heat equation in space using the finite element method and performs the time integration with unconditionally stable implicit time stepping methods. To improve the computational efficiency without sacrificing accuracy, the MTA features adaptive spatiotemporal refinement. The large-scale linear systems that arise during the simulation are solved with fast preconditioned Krylov subspace methods. The MTA supports thermal analysis of realistic integrated systems and surpasses the computational capabilities and performance of existing academic thermal simulators. For example, the simulation of a processor in a package attached to a heat sink, modeled by a computational grid consisting of over 3 million nodes, takes less than 3 min. The MTA is fully parallel and publicly available. 1

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The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems

In this study, the variability of conventional planar (20nm System-on Chip, 20SoC) and FinFET (16nm FinFET, 16FF) time-zero Vt and Bias-Temperature Instability (BTI) induced aging is investigated, as well as its impact on SRAM and Logic product reliability. For 16FF, the Vt after aging is dominated by initial Vt distribution rather than BTI induced Vt shift, and their Vt sigmas are also superior to planar 20SoC. NBTI (Negative Bias Temperature Instability) relaxation between 20SoC and 16FF are comparable, while 16FF shows less PBTI (Positive Bias Temperature Instability) recovery due to the local high field on fin top. Correlation between SRAM static noise margin (SNM) and NBTI induced Vt shift concurs with the domination of initial Vt sigma for SNM drift. Chip and bit level High-Temperature Operating Life (HTOL) burn-in test with recovery phases demonstrates all the recovery occurs right after stress, so there is no Vt mismatch to make more Vmin tailing. Bit level AC and DC HTOL Vmin sigma concurs with the additional Vt mismatch by DC stress. Logic Vmin recovery at higher temperature demonstrates the signature of BTI contribution in Vmin. These results indicate that even some of the BTI features of 16FF are different from 20SoC, the adequate process optimization for initial Vt sigma tightening still dominates SRAM/Logic HTOL Vmin shift rather than BTI aging.

Consideration of BTI variability and product level reliability to expedite advanced FinFET process development

The increasing power density in modern highperformance multi-processor system-on-chip (MPSoC) is fueling a revolution in thermal management. On the one hand, thermal phenomena are becoming a critical concern, making accurate and efficient simulation a necessity. On the other hand, a variety of physically heterogeneous solutions are coming into play: liquid, evaporative, thermoelectric cooling, and more. A new generation of simulators, with unprecedented flexibility, is thus required. In this paper, we present 3D-ICE 3.0, the first thermal simulator to allow for accurate nonlinear descriptions of complex and physically heterogeneous heat dissipation systems, while preserving the efficiency of latest compact modeling frameworks at the silicon die level. 3D-ICE 3.0 allows designers to extend the thermal simulator with new heat sink models while simplifying the time-consuming step of model validation. Support for nonlinear dynamic models is included, for instance to accurately represent variable coolant flows. Our results present validated models of a commercial water heat sink and an air heat sink plus fan that achieve an average error below 1∘C and simulate, respectively, up to 3x and 12x faster than the real physical phenomena.

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3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models

Dynamic Thermal Management (DTM) has become a major challenge since it directly affects Multiprocessors Systems-on-chip (MPSoCs) performance, power consumption, and reliability. In this work, we propose a transient fan model, enabling adaptive fan speed control simulation for efficient DTM. Our model is validated through a thermal test chip achieving less than 2°C error in the worst case. With multiple fan speeds, however, the DTM design space grows significantly, which can ultimately make conventional solutions impractical. We address this challenge through a reinforcement learning-based solution to proactively determine the number of active cores, operating frequency, and fan speed. The proposed solution is able to reduce fan power by up to 40% compared to a DTM with constant fan speed with less than 1% performance degradation. Also, compared to a state-of-the-art DTM technique our solution improves the performance by up to 19% for the same fan power.

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Dynamic thermal management with proactive fan speed control through reinforcement learning

In this article, we propose a fast thermal modeling tool, 3DSim , using a Green’s-function-based approach. Green’s-function-based approaches have been shown to be faster than the traditional finite-difference-based techniques. Our proposed tool can model steady-state and transient thermal profiles for both 2-D and 3-D chips, which may contain multiple active layers and fluid-carrying microchannels for heat removal. The unique advantage of our tool is that it models leakage power analytically using a piecewise-linear leakage model, thereby eliminating the need to iterate multiple times through the leakage–temperature feedback loop. We use several algebraic techniques and transforms to compute the thermal profile analytically and thereby speedup the process of calculation. To the best of our knowledge, transform-based approaches have not been used before to model the temperature in 3-D chips with microchannels. Our approach provides a $150\times $ speedup over state-of-the-art thermal simulators, with an error limited to 5%.

A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips

Thermal analysis is crucial for determining the propagation of heat and tracking the formation of hot spots in advanced integrated circuit technologies. At the core of the thermal analysis for integrated circuits is the numerical solution of the heat equation. Prior academic thermal analysis tools typically compute temperature by applying finite difference methods on uniform grids with time integration methods having fixed time step size. Additionally, the linear systems arising from the discretized heat equation are solved using direct methods based on matrix factorizations. Direct methods, however, do not scale well as the problem size increases. Moreover, most of the tools support only 2-D or a limited number of 3-D technologies. To address these issues, this paper presents a novel thermal analyzer with the ability to model both 2-D and 3-D circuit technologies. The analyzer solves the heat equation using the finite element method for the spatial discretization coupled with implicit time integration methods for advancing the solution in time. It also offers fully adaptive spatio-temporal refinement features for improved accuracy and computational efficiency. The resulting linear systems are solved by a multigrid preconditioned Krylov subspace iterative method, which gives superior performance for 3-D transient analyses. The analyzer is shown to accurately capture the propagation of heat in both the horizontal and vertical directions of integrated systems.

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IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods

Thermal analysis of integrated circuits (IC) is a high performance computing problem because the nanoscale spatiotemporal features of the problem result in a large discrete problem. In previous works, compact models of ICs were introduced to speed up the modeling process. However, such methods have limited accuracy as they approximate the underlying physics. They are also ill-suited to simulate the thermal characteristics of an IC at the cell-level. The finite element method (FEM) is an appropriate computational technique for providing both fast and accurate thermal analyses. Considering that the number of cells in modern ICs is on the order of millions, thermal analysis at this abstraction level is a formidable task. Consequently, handling the computational meshes and computing thermal profiles of an IC at the cell-level requires substantial computing power. In order to provide accurate cell-level thermal simulations at a lower computational cost, this work introduces advanced techniques that judiciously trade off mesh granularity with simulation accuracy which allows fast analysis of cell-level floorplans. The proposed cell-homogenization techniques start with a flat cell-level floorplan and a related power trace and produce reduced order meshes that accelerate thermal simulations with a negligible loss in accuracy. Results show that the proposed techniques achieve up to a 90% reduction in the number of nodes in the mesh with less than 5% error in the temperature compared to the full scale mesh. The simulation time is also reduced by an order of magnitude.

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Scott Ladenheim

Papers

The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems

IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods

Computationally efficient standard-cell FEM-based thermal analysis