Seenu Gopalraju

Bio: Seenu Gopalraju is an academic researcher from Texas Instruments. The author has contributed to research in topics: Low-dropout regulator & Dropout voltage. The author has an hindex of 3, co-authored 4 publications receiving 79 citations.

Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison

Abstract: Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This paper compares CL-LDOs in a unified matter. We designed, fabricated, and tested five illustrative CL-LDO regulator topologies under common design conditions using 0.6?m CMOS technology. We compare the architectures in terms of (1) line/load regulation, (2) power supply rejection, (3) line/load transient, (4) total on-chip compensation capacitance, (5) noise, and (6) quiescent power consumption. Insights on what optimal topology to choose to meet particular LDO specifications are provided.

Multi-stage amplifier

Abstract: In an embodiment, an amplifier includes first, second, and third stages, and a feedback network. The first stage has a first passband and is configured to generate a first output signal in response to first and second input signals, and the second stage has a second passband that is higher in frequency than the first passband and is configured to generate a second output signal in response to third and fourth input signals. The third stage has a first input node coupled to receive the first output signal, a second input node coupled to receive the second output signal, and an output node. And the feedback network is coupled between the second input node and the output node of the third stage. For example, where the first, second, and third stages are respective operational-transconductance-amplifier stages, such an amplifier may be suitable for low-power applications.

An Off-Chip Capacitor Free Low Dropout Regulator with PSR Enhancement at Higher Frequencies

Abstract: An Off-Chip Capacitor Free Low Dropout Regulator with PSR Enhancement at Higher Frequencies. (December 2010) Seenu Gopalraju, B.E., Anna University Chair of Advisory Committee: Dr. Edgar Sanchez-Sinencio Low Dropout Regulators (LDOs) are extensively used in portable applications like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple. In addition to these, the radio circuits in these applications demand high power supply rejection (PSR). The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. Enhanced buffer based compensation is proposed for the fully on-chip CMOS LDO which stabilizes the loop for different load conditions as well as improve the power supply rejection (PSR) until frequencies closer to open loop‟s unity-gain frequency. The stability and PSR are totally valid even for load capacitor varying from 0 to 100 pF. The proposed capacitor-less LDO is fabricated in On-Semi 0.5 μm fully CMOS process. Experimental results confirm a PSR of -30 dB till 420 KHz for the maximum load current of 50mA. The load transients of the chip shows transient glitches less than 90 mV independent of output capacitance.

Method and circuitry for regulating a voltage

Abstract: In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.

An Autonomous Energy Harvesting Power Management Unit With Digital Regulation for IoT Applications

Abstract: Efforts towards energy-harvesting solutions are targeted for wireless sensor node applications and focus on performing maximum power extraction and storing power, yet efforts to deliver a regulated supply to voltage-sensitive blocks in power-limited applications has yet to be fully achieved. This paper presents a low-power, autonomous power management unit (PMU) able to perform maximum power point tracking for dc-type renewable sources. It includes a startup circuit fed directly from the renewable source. The PMU delivers a regulated output voltage through a digital LDO. The main step-up operation is performed through a dynamically controlled, power-aware, capacitive dc–dc converter that performs the required voltage gain procedure. Then, the digital LDO receives the EH source power density information from the dc–dc converter and provides regulation. Information about the source-power density availability is passed on to the digital LDO in order to select the best pass device size from a bank of three arrays. The PMU allows power consumption decrease by reducing the gate driving losses associated with large pass transistor devices, and it enhances efficiency. The system was fabricated in 180 nm CMOS process, and maximum end-to-end efficiency was measured at 57% with 1.75 mW of input power.

A 200-ps-Response-Time Output-Capacitorless Low-Dropout Regulator With Unity-Gain Bandwidth >100 MHz in 130-nm CMOS

Abstract: An output-capacitorless low-dropout regulator (OCL-LDO) using enhanced multipath nested Miller compensation with embedded feedforward path for system-on-chip (SoC) applications is presented in this paper While state-of-the-art LDOs are restricted to low-frequency operation with a maximum unity-gain bandwidth (UGB) typically ranging from several hundred kilohertz to no higher than 10 MHz even in advanced technologies (65 nm or beyond), the prototype fabricated in a standard 130-nm CMOS process features over 100-MHz UGB for all loading conditions up to 25-mA output current while consuming a quiescent current of 112 μ A With this ultra-wide bandwidth, the proposed LDO achieves 200-ps response time for load transient with 300-ps edge time The extension of UGB also magnificently contributes to improvement of power-supply rejection (PSR), making it comparable to OCL-LDOs that use ripple-feedforward techniques to specifically boost PSR or LDOs with large off-chip decoupling capacitors, while enjoying much faster speed The chip area is 0008 mm2

A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads

Abstract: This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18- $\mu \text{m}$ CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency.

A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

Abstract: This paper presents an internally compensated capacitor-less low dropout regulator (CL-LDO) with bulk-driven feed-forward supply noise cancellation and adaptive compensation for fast settling time ( TS ). A feed-forward path from the CL-LDO's supply input to the output is implemented to increase power supply rejection (PSR) from mid-range frequencies to up to 5 MHz. The CL-LDO achieves a −90 dB low frequency and –64 dB PSR at 1 MHz for 50 mA of load current ( IL ). A transconductance amplifier with adaptive Miller compensation based on IL sense is used to increase the unity-gain frequency by 40× at heavy loads. The CL-LDO achieves a 0.3 mV/V line regulation, 10 μ V/mA load regulation, 300 ns of TS , and 0.16 ps figure of merit, which is 7.5× better than current state-of-the-art CL-LDOs. The CL-LDO was fabricated in CMOS 130 nm technology, consumes IQ of 42 μ A, has a dropout voltage ( V DO) of 200 mV for IL of 50 mA, and occupies an active area of 0.0046 mm2.

Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier

Abstract: This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of $10.2~\mu \text{A}$ . It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of $0.22~\mu \text{s}$ is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of $0.1~\mu \text{s}$ .