This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining passive reduced-order macromodels for linear RLC systems. In this paper, PRIMA is demonstrated in terms of a simple implementation which extends the block Arnoldi technique to include guaranteed passivity while providing superior accuracy. While the same passivity extension is not possible for MPVL, comparable accuracy in the frequency domain for all examples is observed.

/pdf/prima-passive-reduced-order-interconnect-macromodeling-4a2e1xctkb.pdf

PRIMA: passive reduced-order interconnect macromodeling algorithm

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail.

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Simulation of high-speed interconnects

Krylov-subspace methods for reduced-order modeling in circuit simulation

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

/pdf/thermal-modeling-analysis-and-management-in-vlsi-circuits-27gdag8m8n.pdf

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

In recent years, reduced-order modelling techniques based on Krylov-subspace iterations, especially the Lanczos algorithm and the Arnoldi process, have become popular tools for tackling the large-scale time-invariant linear dynamical systems that arise in the simulation of electronic circuits. This paper reviews the main ideas of reduced-order modelling techniques based on Krylov subspaces and describes some applications of reduced-order modelling in circuit simulation.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/58CA626CC975F53BD9B5BE76D1B85DF3/S0962492902000120a.pdf/div-class-title-model-reduction-methods-based-on-krylov-subspaces-div.pdf

Model reduction methods based on Krylov subspaces

This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects. >

Time-domain macromodels for VLSI interconnect analysis

Asymptotic waveform evaluation (AWE), which is based upon moment-matching, has been demonstrated as an efficient approach for CAD circuit simulation/analysis. The authors describe an approach for overcoming the inherent instability associated with AWE and moment-matching methods as they apply to circuit analysis problems. The efficiency and accuracy of this algorithm were demonstrated in the analysis of large, lumped RLC interconnect-circuit analysis problems and printed circuit board interconnections. >

On the stability of moment-matching approximations in asymptotic waveform evaluation

Electronic system design requires noise and delay analyses of lossy, low-loss, frequency dependent, and coupled transmission lines, along with lumped parasitic elements. Numerous models and techniques have been developed for simulating these interconnect circuits, however, no single method represents the optimal approach for all transmission line problems. Accuracy and efficiency considerations would suggest the use of different models and analyses for the various types of interconnects. Such an approach to simulating transmission lines requires a measure of goodness for selecting the appropriate model and analysis in terms of the circuit parameters. Toward this goal, this paper presents an efficient methodology for characterizing transmission line models into solution domains. This provides an efficient technique for automatically selecting the type of interconnect model and analysis. Specifically, for a specified acceptable modeling error, analysis domains are established for automatic model selection between the classical method of characteristics, a lumped modeling approach and the state-based convolution technique within a simulation and analysis tool. In general, however, this approach can be applied to any combination of models and analyses, if a measure of accuracy and efficiency can be established.

Domain characterization of transmission line models and analyses

Asymptotic Waveform Evaluation (AWE) has been demonstrated as an efficient approach for interconnect circuit simulation/analysis. However, since it is based upon moment-matching, it is prone to yielding unstable approximations for stable circuits. This paper describes a systematic approach for alleviating the inherent instability associated with AWE and moment-matching methods as they apply to passive, digital, interconnect circuits. The efficiency and accuracy of this approach are demonstrated on several large, RLC interconnect-circuit problems. >

Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications

This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

Seok-Yoon Kim

Papers

Time-domain macromodels for VLSI interconnect analysis

On the stability of moment-matching approximations in asymptotic waveform evaluation

Domain characterization of transmission line models and analyses

Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications

Short circuit power estimation of static CMOS circuits