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Author

Seshadri Gopalan

Bio: Seshadri Gopalan is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Capacitor & Choke. The author has an hindex of 2, co-authored 5 publications receiving 13 citations.
Topics: Capacitor, Choke, Inductor, Ripple, Distortion

Papers
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Journal ArticleDOI
TL;DR: The article proposes the derating of load required to keep the capacitor current within the safe value irrespective of the level of abnormalities and grid impedance.
Abstract: Among the various supply voltage abnormalities, unbalance and distortion are some of the major threats to the dc bus capacitor of adjustable speed drives. The effect of supply voltage unbalance on the dc bus capacitor changes in the presence of supply voltage harmonics. Further, the value of grid impedance and the load on the drive influences the response of these supply voltage abnormalities on the dc bus capacitor. This article analyzes the impact of unbalance, distortion, and simultaneous presence of unbalance and distortion in the supply voltage, on the dc bus capacitor, along with the effect of grid impedance and the load on the drive. As a result of the analysis, the article proposes the derating of load required to keep the capacitor current within the safe value irrespective of the level of abnormalities and grid impedance. The effects are analyzed by simulations and validated by the hardware test setup.

13 citations

Proceedings ArticleDOI
01 Dec 2018
TL;DR: In this paper, the impact of voltage unbalance assessment in estimating their severity for Adjustable Speed Drives (ASDs) has been investigated, where the true unbalance in system voltages, as defined by the ratio of negative to positive sequence is taken as the benchmark to assess the deviation arising out of various definitions.
Abstract: While Voltage Unbalance is quantified by formulae in many standards, all lead to different estimates for a given set of three-phase source voltages. In this paper, we focus on the impact of this unbalance assessment in estimating their severity for Adjustable Speed Drives (ASDs). The true unbalance in system voltages, as defined by the ratio of negative to positive sequence is taken as the benchmark to assess the deviation arising out of various definitions. An estimate of Voltage Unbalance of a large sample of voltage sets through various definitions is compared with the true unbalance. It is shown that this indicates maximum possible errors that may arise when using various definitions. The Total Harmonic Current (THC) and Capacitor Heat i ng Factor (CHF) are then used as indices to assess the severity of a particular voltage combination and it is shown that definitions of unbalance do not lead to clear correlation to the THC and CHF. It is further shown that the quantum of negative sequence is a good measure to assess the severity of an unbalanced supply system for the Adjustable Speed Drive topology considered.

9 citations

Proceedings ArticleDOI
23 Apr 2019
TL;DR: In this article, the authors proposed the use of Crest Factor (CF) and Asymmetry Factor (AF) of the supply voltage to assess the impact of supply voltage harmonics on dc bus capacitor and choke inductor.
Abstract: Though supply voltage distortion is generally measured using Total Harmonic Distortion (THD), the response of voltage distortion on Adjustable Speed Drive (ASD) loads does not show a proper correlation with this measuring index, THD. It is due to the fact that the response not only depends on the harmonic magnitude alone, also the angle of harmonics changes the response. In order to address this issue, this paper proposes the use of Crest Factor (CF) and Asymmetry Factor (AF) of the supply voltage to assess the impact of supply voltage harmonics on dc bus capacitor and choke inductor. The paper focuses on the response of harmonics on the front end of the ASD.

7 citations

Proceedings ArticleDOI
01 Jan 2020
TL;DR: In this article, the effect of sinusoidal balanced fluctuation on dc bus capacitors with inductor placed either in dc-link or ac side was analyzed, and an analytical expression was derived to calculate the magnitude of low frequency component in the capacitor current for a given magnitude and frequency of fluctuation.
Abstract: Supply voltage with low frequency fluctuations will introduce a low (fluctuation) frequency component in the dc link of Adjustable Speed Drives (ASDs), which may increase the net rms current through the DC choke (inductor) and DC-link capacitor. In order to analyze the impact of such low frequency component on the dc-link components (choke and capacitor), performance parameters are considered such as Capacitor Heating Factor (CHF) and total loss for capacitor and choke respectively. The net rms value of capacitor current estimated using appropriate weights of the frequency components is defined as CHF. This paper (a) analyses the effect of sinusoidal balanced fluctuation on dc bus capacitor with inductor placed either in dc-link or ac side, (b) derives an analytical expression to calculate the magnitude of low frequency component in the capacitor current for a given magnitude and frequency of fluctuation, (c) analyses the impact of unbalanced fluctuation in supply voltage which introduces further low frequency components in the capacitor current resulting in increased CHF and (d) proposes a new index to calculate the fluctuation effect on dc bus capacitor, as the existing indices do not correlate with the effects. As a result, it is also found that, (a) the increase of CHF due to balanced voltage fluctuation is the same with the presence of dc and ac inductor and (b) unbalanced fluctuation effect on CHF is rather more compared to balanced fluctuation, considering the practical level of fluctuation unbalance observed at industrial sites.

1 citations

Proceedings ArticleDOI
16 Dec 2020
TL;DR: In this paper, the difference in the DC bus capacitor ripple current values between the two topologies for a given grid disturbance condition was identified, and it was found that the DC choke topology is better in terms of the stress on DC bus capacitance under balanced, unbalanced, and distorted grid conditions, considering the practical field data.
Abstract: Commonly available adjustable speed drives with diode bridge front end usually employ an inductor either in the AC side (line choke) or in the DC side (DC choke). While both the topologies are commercially popular, the difference between their performances under grid disturbances is of interest. It is identified that there exists a difference in the DC bus capacitor ripple current values between these topologies, for a given grid disturbance condition. However, both the topologies result, approximately, in the same amount of ripple in the torque for most of the cases, irrespective of the grid disturbances (up to the level of disturbance considered). It is found that the DC choke topology is better in terms of the stress on the DC bus capacitor under balanced, unbalanced, and distorted grid conditions, considering the practical field data.

1 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, a multi-objective control scheme that simultaneously ensures elimination of the collective APOs/RPOs at point of common coupling (PCC), overcurrent protection and reactive power injection is presented.
Abstract: The growing interest in connecting more distributed generation (DG) units to the utility grid, microgrids deal with the various challenges to satisfy a sufficient level of ancillary services such as active power oscillations (APOs), reactive power oscillations (RPOs), fault ride-through (FRT) capability, and overcurrent problem. Hence, for parallel operated grid-connected inverters (GCIs) based MG, this study presents a multi-objective control scheme that simultaneously ensures elimination of the collective APOs/RPOs at point of common coupling (PCC), overcurrent protection and reactive power injection. One of the significant parts of this study compared with similar existing studies is that provides reactive power support capability to fulfil the FRT requirements of the grid-connected multi-DG units and to remain grid-connected during asymmetrical grid faults. A current restraining control is also presented to ensure the safe operation of the MG system and to avoid overcurrent. The cancellation of the collective APOs and RPOs at the PCC for parallel operation of the GCIs has been achieved by using adjustable control coefficients and demonstrated with theoretical analyses in detail. Extensive case studies are presented and discussed to demonstrate the performance of the proposed ideas and to meet the shortcomings of the previous studies.

19 citations

Journal ArticleDOI
TL;DR: The article proposes the derating of load required to keep the capacitor current within the safe value irrespective of the level of abnormalities and grid impedance.
Abstract: Among the various supply voltage abnormalities, unbalance and distortion are some of the major threats to the dc bus capacitor of adjustable speed drives. The effect of supply voltage unbalance on the dc bus capacitor changes in the presence of supply voltage harmonics. Further, the value of grid impedance and the load on the drive influences the response of these supply voltage abnormalities on the dc bus capacitor. This article analyzes the impact of unbalance, distortion, and simultaneous presence of unbalance and distortion in the supply voltage, on the dc bus capacitor, along with the effect of grid impedance and the load on the drive. As a result of the analysis, the article proposes the derating of load required to keep the capacitor current within the safe value irrespective of the level of abnormalities and grid impedance. The effects are analyzed by simulations and validated by the hardware test setup.

13 citations

Proceedings ArticleDOI
25 Sep 2020
TL;DR: In this paper, a frequency coupling matrix is proposed to model a three phase Variable Frequency Drive (VFD) for balanced harmonic simulations, which is obtained by performing a fingerprint scan on the time domain model built in simulation and validated with a commercial VFD in the lab.
Abstract: This paper proposes a frequency coupling matrix to model a three phase Variable Frequency Drive (VFD) for balanced harmonic simulations. The model is obtained by performing a fingerprint scan on the time domain model built in simulation and validated with a commercial VFD in the lab. The characteristics of the matrix obtained are discussed in the paper. The response obtained from the matrix model is analyzed and compared with the one obtained from time domain model for different distortion levels of the applied voltage. The voltage waveforms are constructed with various combinations of harmonics having different magnitude and phase angle combinations, as observed from the field measurement in various locations in India. It is shown that the response obtained from the matrix model matches closely with that obtained from the time domain simulation of the VFD.

6 citations

Proceedings ArticleDOI
16 Dec 2020
TL;DR: In this article, the analysis of real-time power quality data collected for 50 days at a domestic site in India was performed using a dedicated PQ analyzer, and the measurement and analysis were performed to identify the level of different grid disturbances and compared with relevant standards.
Abstract: This paper presents the analysis of real time power quality data collected for 50 days at a domestic site in India. The data is collected using a dedicated PQ analyzer. The measurement and analysis are performed to identify the level of different grid disturbances and compared with relevant standards. Voltage unbalance and individual voltage harmonics are observed to be the major disturbances. In addition, the analysis of different kinds of loads, including new technology loads, present at the house is performed by recording the current waveforms drawn by these loads. The incoming supply voltage and current of the neighbouring houses are also recorded. An aggregate load model is presented based on the measurements performed at different houses connected to the same feeder.

5 citations

Proceedings ArticleDOI
01 Mar 2020
TL;DR: Several existing three-phase delta voltages’ unbalance factors, including the "true un balance factor" (the negative sequence voltage unbalance factor) and its complex form, are considered and new geometric criteria of delta voltage’ balance and unbalance, based on the dealing with delta voltaged triangles of equal perimeters and different areas are offered.
Abstract: Several existing three-phase delta voltages’ unbalance factors, including the "true unbalance factor" (the negative sequence voltage unbalance factor) and its complex form, are considered. New geometric criteria of delta voltages’ balance and unbalance, based on the dealing with delta voltages’ triangles of equal perimeters and different areas are offered. All the unbalance factors are shown in their dependences on one particular phase voltage (and also on one particular delta voltage), separately on the magnitude (for the case of a single-phase magnitude unbalance) and on the initial phase angle value (for the case of a single-phase angle unbalance). Also the fragment of a LabVIEW virtual instrument for the assessment of the negative sequence voltage unbalance factor and the new geometric factors is offered.

3 citations