Seung-Ho Jung

Bio: Seung-Ho Jung is an academic researcher from Soongsil University. The author has contributed to research in topics: Low-power electronics & Electronic circuit. The author has an hindex of 1, co-authored 1 publications receiving 17 citations.

Short circuit power estimation of static CMOS circuits

Abstract: This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

Abstract: The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

Analytical transient response and propagation delay model for nanoscale CMOS inverter

Abstract: This paper presents a new analytical propagation delay model for nanoscale CMOS inverters. By using a non-saturation current model, the analytical input-output transfer responses and propagation delay model are derived. The model is used for calculating inverter delays for different input transition times, load capacitances and supply voltages. Delays predicted by the proposed model are in good agreement with those of transistor level simulation results from SPICE, with accuracy of 3% or better.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.

Abstract: The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.

Modélisation et optimisation de la consommation énergétique d'un système de communication Wi-Fi

Abstract: La forte augmentation du nombre de terminaux connectes ces dernieres annees et l'utilisation croissante des technologies de communication impacte de maniere non negligeable la facture energetique. Pour enrayer cette augmentation de la consommation energetique, il devient primordial de pouvoir comparer en termes de consommation les algorithmes de communications numeriques, afin de developper l'architecture de transmission la moins energivore. Dans cette these, la couche physique des standards Wi-Fi IEEE 802.11ac est analysee sous un angle energetique. La puissance dissipee dans les circuits pour faire fonctionner les algorithmes de traitement de signal est prise en compte en plus de la puissance d'emission d'antenne classique. La methodologie mise en œuvre inclut a la fois des simulations et des developpements sur plateforme materielle (FPGA), permettant d'obtenir des evaluations de la consommation plus realistes. Nous avons dans un premier temps analyse de facon isolee les elements composant les chaines de communications numeriques. Puis nous avons integre les periodes d'activite et d'inactivite de chaque element dans le calcul de la consommation energetique globale des chaines. Nous proposons une methode pratique et efficace d'estimation de la consommation, incluant une base de donnees issue de simulations, et une analyse theorique des taux d'activite de chaque element de la chaine. Ces resultats permettent d'analyser la repartition de la consommation en puissance des elements composant les emetteurs et les recepteurs, et de comparer diverses architectures et jeux de parametres. En particulier, nous avons evalue l'impact de deux architectures de Transformees de Fourier Rapides sur la consommation globale du systeme.