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Seung Mo Kim

Bio: Seung Mo Kim is an academic researcher from Gwangju Institute of Science and Technology. The author has contributed to research in topics: Ternary operation & Materials science. The author has an hindex of 4, co-authored 17 publications receiving 69 citations. Previous affiliations of Seung Mo Kim include Pohang University of Science and Technology.

Papers
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Journal ArticleDOI
TL;DR: A ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit, is demonstrated.
Abstract: Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

47 citations

01 Jan 2010
TL;DR: In this paper, sociolinguistic research conducted among speakers of five AustroAsiatic language varieties in northwest Bangladesh: Koda, Kol, Mahali, Mundari, and Santali is reported.
Abstract: This paper reports on sociolinguistic research conducted among speakers of five AustroAsiatic language varieties in northwest Bangladesh: Koda, Kol, Mahali, Mundari, and Santali. These are collectively referred to as the Santali Cluster because Santali is the most populous and developed language among these five varieties. Linguistic variation within and across these varieties, long-term viability of each variety, and attitudes of speakers towards their own and other language varieties were investigated. The degree of intelligibility in Santali by speakers of the other varieties and the bilingual ability in Bangla of speakers from each variety were also studied. This research was carried out from November 2004 through January 2005 through the use of word lists, questionnaires, a Bangla Sentence Repetition Test, and stories recorded in Santali, Mundari, and Mahali.

9 citations

Journal ArticleDOI
TL;DR: In this article, hot-carrier instability under stress conditions emulating a random logic operation (random ON and OFF) has been investigated using pseudorandom bit sequence (PRBS) stress patterns.
Abstract: Hot-carrier instability under stress conditions emulating a random logic operation (random ON and OFF) has been investigated using pseudorandom bit sequence (PRBS) stress patterns. Furthermore, the impacts of PRBS stress on circuit-level operation have been compared with the conventional dc (static) and ac (periodic) stress conditions using hot-carrier-induced random timing jitter. It was observed that the recovery achieved by charge trapping and detrapping under dynamic stress conditions significantly affects the degree of hot-carrier degradation.

7 citations

Journal ArticleDOI
TL;DR: High-pressure annealing in oxygen ambient at low temperatures (∼300 °C) was effective in improving the performance of graphene field-effect transistors and the field- effect mobility was improved by 45% and 83% for holes and electrons.
Abstract: High-pressure annealing in oxygen ambient at low temperatures (∼300 °C) was effective in improving the performance of graphene field-effect transistors. The field-effect mobility was improved by 45% and 83% for holes and electrons, respectively. The improvement in the quality of Al2O3 and the reduction in oxygen-related charge generation at the Al2O3-graphene interface, are suggested as the reasons for this improvement. This process can be useful for the commercial implementation of graphene-based electronic devices.

6 citations


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Journal ArticleDOI
TL;DR: In this article, the authors describe the physics, technology, and reliability of GaN-based power devices, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field.
Abstract: Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

141 citations

Journal ArticleDOI
01 Jul 2019
TL;DR: In this article, a ternary CMOS inverter based on a single threshold voltage and a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling is presented.
Abstract: The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary metal–oxide–semiconductor (CMOS) processes.

68 citations

Journal ArticleDOI
TL;DR: The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs and is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternARY logic.
Abstract: We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

64 citations