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Author

Seyeon Yoo

Bio: Seyeon Yoo is an academic researcher from Ulsan National Institute of Science and Technology. The author has contributed to research in topics: Jitter & Phase-locked loop. The author has an hindex of 9, co-authored 18 publications receiving 258 citations.

Papers
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Journal ArticleDOI
TL;DR: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltagetemperature (PVT)-calibration is presented.
Abstract: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was $\text {0.06 mm}^{2}$ and total power consumption was 9.5 mW.

80 citations

Journal ArticleDOI
TL;DR: An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented and is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion.
Abstract: An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 $\mu \text{W}$ to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was −129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were −39.1 dBc and 86 fs, respectively.

50 citations

Proceedings ArticleDOI
25 Feb 2016
TL;DR: An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption, but its jitter performance is sensitive to process, voltage, and temperature (PVT) variations.
Abstract: An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an ILCM has a critical problem in that its jitter performance is sensitive to process, voltage, and temperature (PVT) variations. Thus, in general, an ILCM must be equipped with a dedicated PVT-calibrator to mitigate the sensitivity of its performance to PVT variations. One of the most general calibration methods is to use a phase-locked loop (PLL). This method can correct static frequency deviations of a voltage-controlled oscillator (VCO) due to process variations, but it cannot prevent real-time frequency drifts due to temperature or voltage variations [1]. Recently, many efforts have been made to develop new PVT-calibrators, capable of continuous frequency tracking [1–6]. In [1–3], frequency drifts were monitored by a replica-VCO or a delay-locked loop (DLL) that used the same delay cells as the main VCO. However, in these architectures, each calibrator must spend the same amount of the power as the VCO. In addition, mismatches between delay cells limit the calibrating precision or demand an additional calibrating step. References [4–6] presented frequency-tracking loops (FTLs) based on various methods to detect the phase shifts of VCO outputs when reference-pulses are injected. Reference [4] used a time-to-digital converter (TDC) to detect the phase shifts, but it had large power consumption and silicon area due to the many digital circuits. Although the FTL of [5] used a timing-adjusted phase detector (PD), it could suffer from large in-band noise or spurs since the switches of the charge pump (CP) must be on for a considerable duration in every period. In [6], a pulse-gating technique that periodically skipped the injection was presented, but it could generate fractional spurs.

34 citations

Proceedings ArticleDOI
01 Feb 2017
TL;DR: To meet requirements of high data-rates, RF transceivers for a 5G standard must have an ultra-wide bandwidth in a mm-wave band, and an injection-locked frequency multiplier (ILFM) is an attractive solution, achieving ultra-low PN even in a tight power budget.
Abstract: To meet requirements of high data-rates, RF transceivers for a 5G standard must have an ultra-wide bandwidth in a mm-wave band. A big challenge of a 5G transceiver is to generate ultra-low-PN (phase noise) local-oscillator (LO) signals to suppress integrated PN (IPN) over such an extremely wide bandwidth. A PLL that directly generates mm-band LO signals is not a good choice due to power-hungry frequency dividers and relatively poor PN. An mm-band LO generator, cascading a GHz-range PLL and a frequency multiplier as shown in Fig. 19.2.1, is an attractive solution. First, a GHz-range PLL can have a higher FOM than a mm-band PLL [1]. Second, the cascaded architecture is naturally able to support the bands for 2G to 4G standards. An injection-locked frequency multiplier (ILFM) is popular in a mm-band, achieving ultra-low PN even in a tight power budget. However, the vulnerability of PN to PVT variations is a critical problem. For an ILFM, the PN performance can be improved only when the free-running VCO frequency, f VCO , and the target frequency are sufficiently close within the lock range, f L , which is very narrow, especially, at high frequencies. To calibrate f VCO over PVT, many frequency-tracking loops (FTLs) have used a power-hungry circuit (such as a replica-VCO, a TDC, and a counter) operating at f VCO , but they were not suitable for a mm-band ILFM. The sub-sampling FTL [2] used the voltage levels of the VCO outputs, momentarily sampled by injection pulses. However, for the accurate sampling, the pulse width of the injection pulses must be very narrow, since the sampling occurs at the edges of the pulses. For a mm-band VCO, the pulse width must be less than 10ps, but these narrow pulses limit the injection strength and f L . In the mm-band ILFM of [3], the mixers and dividers consumed a lot of power. An envelope detector was used for another mm-band ILFM to enable the calibration operating at low frequencies [4], but it cannot detect f VCO after the VCO is injection-locked and prevent PN degradation due to real-time drifts of f VCO .

28 citations

Journal ArticleDOI
TL;DR: This paper presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur and proposes a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier.
Abstract: A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability of suppressing jitter of a VCO, we propose a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier. By the proposed FPEC technique, accumulated jitter of a VCO can be removed intensively in a short interval, thereby suppressing jitter dramatically. Based on a PLL topology having an intrinsic integrator in a VCO, the proposed architecture can also achieve a low reference spur despite a high multiplication factor (i.e., 64). This paper also presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur. The proposed PLL was fabricated in a 65-nm CMOS process. The measured rms jitter integrated from 1 kHz to 80 MHz and the reference spur of the output signal with a 3.008-GHz frequency were 357 fs and −71 dBc, respectively. The total active area was 0.047 mm2, and the power consumption was 4.6 mW.

28 citations


Cited by
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Proceedings Article
01 Jan 2008
TL;DR: In this article, the authors present a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve sub-picosecond jitter performance.
Abstract: This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

100 citations

Journal ArticleDOI
TL;DR: The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur.
Abstract: An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm2.

82 citations

Journal ArticleDOI
TL;DR: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltagetemperature (PVT)-calibration is presented.
Abstract: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was $\text {0.06 mm}^{2}$ and total power consumption was 9.5 mW.

80 citations

Journal ArticleDOI
TL;DR: Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog- to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs.
Abstract: A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a −78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM $4 \times 4$ MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm2.

52 citations

Journal ArticleDOI
TL;DR: An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented and is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion.
Abstract: An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 $\mu \text{W}$ to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was −129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were −39.1 dBc and 86 fs, respectively.

50 citations