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Shabnam Mardani

Bio: Shabnam Mardani is an academic researcher from Uppsala University. The author has contributed to research in topics: Engineering & Electromigration. The author has an hindex of 5, co-authored 8 publications receiving 53 citations.

Papers
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TL;DR: Silicon carbide integrated circuits have been suggested for extreme environment operation as discussed by the authors. But the challenge of a new technology is to develop process flow, circuit models and circuit designs for extreme environments operation.
Abstract: Silicon carbide (SiC) integrated circuits have been suggested for extreme environment operation. The challenge of a new technology is to develop process flow, circuit models and circuit designs for ...

32 citations

Journal ArticleDOI
Shabnam Mardani1, Hans Norström1, Ulf Smith1, Jörgen Olsson1, Shi-Li Zhang1 
TL;DR: In this paper, different combinations of Ta and TaN layers are evaluated electrically and morphologically after high-temperature treatments, and the experimental observations are interpreted in terms of Cu grain growth, Ta segregation in the Cu grain boundaries and morphological degradation of the Cu film.

9 citations

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TL;DR: Although wide band gap devices (WBG, e.g. GaN and SiC) are eminently suitable for high temperatures and harsh environments, these properties cannot be fully taken advantage of without an appropriat...

7 citations

Journal ArticleDOI
TL;DR: In this article, different metal stack combinations were used to achieve high-temperature stability of Cu-based interconnects, which is of technological importance for electronic circuits based on wide band gap semiconductors.
Abstract: High-temperature stability of Cu-based interconnects is of technological importance for electronic circuits based on wide band gap semiconductors. In this study, different metal stack combinations ...

7 citations

Journal ArticleDOI
TL;DR: In this article, the β-to-α phase transition in the underlying Ta barrier layer is identified as the major cause responsible for the morphological instability observed above 600°C, which can be avoided using a stacked Ta/TaN barrier.
Abstract: Wide-bandgap (WBG) semiconductor technologies are maturing and may provide increased device performance in many fields of applications, such as high-temperature electronics. However, there are still issues regarding the stability and reliability of WBG devices. Of particular importance is the high-temperature stability of interconnects for electronic systems based on WBG-semiconductors. For metallization without proper encapsulation, morphological degradation can occur at elevated temperatures. Sandwiching Ag films between Ta and/or TaN layers in this study is found to be electrically and morphologically stabilize the Ag metallization up to 800 °C, compared to 600 °C for uncapped films. However, the barrier layer plays a key role and TaN is found to be superior to Ta, resulting in the best achieved stability, whereas the difference between Ta and TaN caps is negligible. The β-to-α phase transition in the underlying Ta barrier layer is identified as the major cause responsible for the morphological instability observed above 600 °C. It is shown that this phase transition can be avoided using a stacked Ta/TaN barrier.

5 citations


Cited by
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Journal ArticleDOI
TL;DR: Silicon carbide integrated circuits have been suggested for extreme environment operation as discussed by the authors. But the challenge of a new technology is to develop process flow, circuit models and circuit designs for extreme environments operation.
Abstract: Silicon carbide (SiC) integrated circuits have been suggested for extreme environment operation. The challenge of a new technology is to develop process flow, circuit models and circuit designs for ...

32 citations

Journal ArticleDOI
TL;DR: This study provides and validate a comprehensive set of models alongside with their parameters for bulk 3C–SiC and revealed that the proposed models are in a very good agreement to experimental data and confidence ranges were identified.
Abstract: The cubic form of SiC (β- or 3C-) compared to the hexagonal α-SiC polytypes, primarily 4H- and 6H–SiC, has lower growth cost and can be grown heteroepitaxially in large area silicon (Si) wafers which makes it of special interest. This in conjunction with the recently reported growth of improved quality 3C–SiC, make the development of devices an imminent objective. However, the readiness of models that accurately predict the material characteristics, properties and performance is an imperative requirement for attaining the design and optimization of functional devices. The purpose of this study is to provide and validate a comprehensive set of models alongside with their parameters for bulk 3C–SiC. The validation process revealed that the proposed models are in a very good agreement to experimental data and confidence ranges were identified. This is the first piece of work achieving that for 3C–SiC. Considerably, it constitutes the necessary step for finite element method simulations and technology computer aided design.

27 citations

Journal ArticleDOI
TL;DR: In this article, the authors present a review of high-k and low-k dielectric materials and their application in various metal-insulator-metal (MIM) structures such as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements.
Abstract: High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges.We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling.We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful”requirements for the various enabling dielectric hard mask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements.We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.© 2019 The Electrochemical Society.

24 citations

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TL;DR: In this article, the ASM-GaN compact model has been enhanced to model the GaN high electron mobility transistors (HEMTs) at extreme temperature conditions, in particular, the temperature dependence of the trapping behavior has been considered.
Abstract: The industry standard advanced SPICE model (ASM)-GaN compact model has been enhanced to model the GaN high electron mobility transistors (HEMTs) at extreme temperature conditions. In particular, the temperature dependence of the trapping behavior has been considered and a simplifying approximation in the temperature modeling of the saturation voltage in the ASM-GaN model has been relaxed. The enhanced model has been validated by comparing the simulation results of the model with the dc ${I}$ – ${V}$ measurement results of a GaN HEMT measured with chuck temperatures ranging from 22 °C to 500 °C. A detailed description of the modeling approach is presented. The new formulation of the ASM-GaN compact model can be used to simulate the circuits designed for extreme temperature environments.

21 citations

Journal ArticleDOI
TL;DR: In this paper, high-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated and three different sizes are optimized in terms of emitter finger width and length and the device layout to have higher current density, lower on-resistance (RON), and more uniform current distribution.
Abstract: High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain ( $\beta $ ) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

19 citations