There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

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Nanoscale thermal transport. II. 2003–2012

The smart grid concept continues to evolve and various methods have been developed to enhance the energy efficiency of the electricity infrastructure. Demand Response (DR) is considered as the most cost-effective and reliable solution for the smoothing of the demand curve, when the system is under stress. DR refers to a procedure that is applied to motivate changes in the customers' power consumption habits, in response to incentives regarding the electricity prices. In this paper, we provide a comprehensive review of various DR schemes and programs, based on the motivations offered to the consumers to participate in the program. We classify the proposed DR schemes according to their control mechanism, to the motivations offered to reduce the power consumption and to the DR decision variable. We also present various optimization models for the optimal control of the DR strategies that have been proposed so far. These models are also categorized, based on the target of the optimization procedure. The key aspects that should be considered in the optimization problem are the system's constraints and the computational complexity of the applied optimization algorithm.

A Survey on Demand Response Programs in Smart Grids: Pricing Methods and Optimization Algorithms

Introduction to heat transfer

Approximate Logic Synthesis (ALS) is the process of synthesizing and mapping a given Boolean network to a library of logic cells so that the magnitude/rate of error between outputs of the approximate and initial (exact) Boolean netlists is bounded from above by a predetermined total error threshold. In this paper, we present Q-ALS, a novel framework for ALS with focus on the technology mapping phase. Q-ALS incorporates reinforcement learning and utilizes Boolean difference calculus to estimate the maximum error rate that each node of the given network can tolerate such that the total error rate at non of the outputs of the mapped netlist exceeds a predetermined maximum error rate, and the worst case delay and the total area are minimized. Maximum Hamming Distance (MHD) between exact and approximate truth tables of cuts of each node is used as the error metric. In Q-ALS, a Q-Learning agent is trained with a sufficient number of iterations aiming to select the fittest values of MHD for each node, and in a cut-based technology mapping approach, the best supergates (in terms of delay and area, bounded further by the fittest MHD) are selected towards implementing each node. Experimental results show that having set the required accuracy of 95% at the primary outputs, Q-ALS reduces the total cost in terms of area and delay by up to 70% and 36%, respectively, and also reduces the run-time by 2.21 times on average, when compared to the best state-of-the-art academic ALS tools.

Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach

Artificial Neural Networks (ANNs) play a key role in many machine learning (ML) applications but poses arduous challenges in terms of storage and computation of network parameters. Memristive crossbar arrays (MCAs) are capable of both computation and storage, making them promising for in-memory computing enabled neural network accelerators. At the same time, the presence of a significant amount of zero weights in ANNs has motivated research in a variety of parameter reduction techniques. However, for crossbar based architectures, the study of efficient methods to take advantage of network sparsity is still in the early stage. This paper presents CSrram, an efficient ex-situ training framework for hybrid CMOS-memristive neuromorphic circuits. CSrram includes a pre-defined block diagonal clustered (BDC) sparsity algorithm to significantly reduce area and power consumption. The proposed framework is verified on a wide range of datasets including MNIST handwritten recognition, fashion MNIST, breast cancer prediction (BCW), IRIS, and mobile health monitoring. Compared to state of the art fully connected memristive neuromorphic circuits, our CSrram with only 25% density of weights in the first junction, provides a power and area efficiency of 1.5x and 2.6x (averaged over five datasets), respectively, without any significant test accuracy loss.

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity

Cloud computing has drawn significant attention from both academia and industry as an emerging computing paradigm where data, applications, or processing power are provided as services through the Internet. Cloud computing extends the existing computing infrastructure owned by the cloud service providers (CSPs) to achieve the economies of scale through virtualization and aggregated computing resources. End users, on the other hand, can reach these services through an elastic utility computing environment with minimal upfront investment. Nevertheless, pervasive use of cloud computing and the resulting rise in the number of data centers have brought forth concerns about energy consumption and carbon emission. Therefore, this paper addresses the problem of resource provisioning and task scheduling on a cloud platform under given service level agreements, in order to minimize the electric bills and maximize the profitability for the CSP. User task graphs and dependencies are randomly generated, whereas user requests for CPU and memory resources are extracted from the Google cluster trace. A general type of dynamic pricing scenario is assumed where the energy price is both time-of-use and total power consumption-dependent. A negotiation-based iterative approach has been proposed for the resource provisioning and task scheduling that is inspired by a routing algorithm. More specifically, in each iteration, decisions made in the previous iteration are ripped-up and re-decided, while a congestion model is introduced to dynamically adjust the resource provisioning decisions and the schedule of each task based on the historical results as well as the current state of affairs. Experimental results demonstrate that the proposed algorithm achieves up to 63% improvement in the total electrical energy bill of an exemplary data center compared to the baseline.

Negotiation-based resource provisioning and task scheduling algorithm for cloud systems

The miniaturization of transistors down to 5nm and beyond, plus the increasing complexity of integrated circuits, significantly aggravate short channel effects, and demand analysis and optimization of more design corners and modes. Simulators need to model output variables related to circuit timing, power, noise, etc., which exhibit nonlinear behavior. The existing simulation and sign-off tools, based on a combination of closed-form expressions and lookup tables are either inaccurate or slow, when dealing with circuits with more than billions of transistors. In this work, we present CSM-NN, a scalable simulation framework with optimized neural network structures and processing algorithms. CSM-NN is aimed at optimizing the simulation time by accounting for the latency of the required memory query and computation, given the underlying CPU and GPU parallel processing capabilities. Experimental results show that CSM-NN reduces the simulation time by up to 6× compared to a state-of-the-art current source model based simulator running on a CPU. This speedup improves by up to 15× when running on a GPU. CSM-NN also provides high accuracy levels, with less than 2% error, compared to HSPICE.

CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach

The down scaling of feature sizes and higher process variations in future CMOS nano-technologies are anticipated to introduce higher manufacturing anomalies. On the other hand designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. These phenomena significantly reduce the functional yield. Redundancy has been used for a long time in regular structures such as memory to tolerate defects; however, for typical irregular logic circuits this would be very challenging. In this paper we introduce a theory that justifies the necessity of using redundancy at sub-chip level of granularity to maximize yield/area (number of healthy dies) for future technologies with higher defect rates. In addition, redundancy at finer levels of granularity, aggravates the overheads of interconnect (steering logics, i.e., forks, joins and switches) such as yield, area, and testing overheads. These overheads limit the level of granularity for logic replication. Current yield estimators are generally pessimistic for interconnects because they do not take circuit and logic context into consideration, and/or they assume all defects are killer-defects, i.e., always result in unacceptable circuit behavior. In this paper we propose a CAD tool to compute the functional yield of the configurable and testable steering logics using (i) actual layout geometries, and (ii) factory data related to density and size of opens (missing metal), shorts (extra metal) and open vias. The experimental results show that our theory of redundancy considering the overheads of steering logics can improve the yield/area by 2.8 times for a real highly-defected circuit (OpenSparc T2 core).

Shahin Nazarian

Papers

Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity

Negotiation-based resource provisioning and task scheduling algorithm for cloud systems

CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach

Theory of redundancy for logic circuits to maximize yield/area