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Shahin Nazarian

Researcher at University of Southern California

Publications -  127
Citations -  1854

Shahin Nazarian is an academic researcher from University of Southern California. The author has contributed to research in topics: Logic gate & Smart grid. The author has an hindex of 18, co-authored 121 publications receiving 1420 citations. Previous affiliations of Shahin Nazarian include Magma Design Automation.

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Journal ArticleDOI

A Majority Logic Synthesis Framework For Single Flux Quantum Circuits

TL;DR: In this article , the authors present a novel SFQ logic synthesis framework that given a netlist, offers an automated mapping solution including majority (MAJ) logic with the goal of minimizing the number of Josephson Junctions (JJs) in the circuits, while catering to the unique characteristics and requirements of the design.
Posted Content

Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space

TL;DR: This work proposes a method that replaces the augmentation in the raw input space with an approximate one that acts purely in the embedding space, and results show that the proposed method drastically reduces the computation, while the accuracy of models is negligibly compromised.
Posted Content

CSM-NN: Current Source Model Based Logic Circuit Simulation -- A Neural Network Approach

TL;DR: CSM-NN as discussed by the authors is a scalable simulation framework with optimized neural network structures and processing algorithms, aimed at optimizing the simulation time by accounting for the latency of the required memory query and computation, given the underlying CPU and GPU parallel processing capabilities.
Journal ArticleDOI

End-to-end Mapping in Heterogeneous Systems Using Graph Representation Learning

TL;DR: The current monolithic programming models and task mapping to compute engines do not fully exploit the recent architectural innovations and can exacerbate the load imbalance and communication inefficiencies.
Proceedings ArticleDOI

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

TL;DR: An effective design framework of FinFET standard cells based on the adaptive independent gate control method such that they can operate properly at all of subthreshold, near-th threshold and super-threshold regions is proposed.