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Shahin Nazarian

Researcher at University of Southern California

Publications -  127
Citations -  1854

Shahin Nazarian is an academic researcher from University of Southern California. The author has contributed to research in topics: Logic gate & Smart grid. The author has an hindex of 18, co-authored 121 publications receiving 1420 citations. Previous affiliations of Shahin Nazarian include Magma Design Automation.

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Gain-based Cell Delay Modeling

TL;DR: In this paper, a gain-based cell delay modeling technique for accurate computation of the electrical output waveform of a CMOS logic cell under a noisy input waveform is presented.
Proceedings ArticleDOI

STAX: Statistical Crosstalk Target Set Compaction

TL;DR: Experimental results on ISCAS'85 benchmark demonstrate that STAX greatly improves the runtime compared to other crosstalk target pruning methodologies, including ATPG, with no prior target set compaction.
Posted Content

VRoC: Variational Autoencoder-aided Multi-task Rumor Classifier Based on Text

TL;DR: Zhang et al. as discussed by the authors proposed a tweet-level variational autoencoder-based rumor classification system, which consists of a co-train engine that trains variational auto-encoders and rumor classification components.
Proceedings ArticleDOI

Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems

TL;DR: This paper investigates the application of power gating to FinFET circuits operating in near- and super-threshold voltage regimes for embedded system applications and proposes a joint optimization algorithm to determine the width/length, position and threshold type of the sleep transistor.