S
Shahin Nazarian
Researcher at University of Southern California
Publications - 127
Citations - 1854
Shahin Nazarian is an academic researcher from University of Southern California. The author has contributed to research in topics: Logic gate & Smart grid. The author has an hindex of 18, co-authored 121 publications receiving 1420 citations. Previous affiliations of Shahin Nazarian include Magma Design Automation.
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Proceedings ArticleDOI
An efficient current-based logic cell model for crosstalk delay analysis
TL;DR: Imodel is presented, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than N LDM-based cell delay models, with a maximum runtime penalty of 19% compared to NLDm-basedcell delay models on medium sized industrial designs.
Journal ArticleDOI
An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes
TL;DR: A device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- and super-threshold operation regimes is presented.
Journal ArticleDOI
CTS2M: concurrent task scheduling and storage management for residential energy consumers under dynamic energy pricing
TL;DR: This study addresses the problem of concurrent task scheduling and storage management for residential energy consumers with PV and storage systems, in order to minimise the electric bill using a negotiation-based iterative approach and a near-optimal storage control algorithm.
Journal ArticleDOI
An optimal energy co-scheduling framework for smart buildings
TL;DR: This paper addresses the co-scheduling problem of HVAC control and HEES system management to achieve energy-efficient smart buildings, while also accounting for the degradation of the battery state-of-health during charging and discharging operations (which determines the amortized cost of owning and utilizing a battery storage system).
Proceedings ArticleDOI
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique
TL;DR: It is demonstrated that, compared to Dual-VT, GLB is a more suitable technique for the advanced 7nm FinFET technology due to its capability of delivering a finer-grained trade-off between the leakage power and circuit speed, not to mention the lower manufacturing cost.