Author
Shakti Singh Chauhan
Other affiliations: Iowa State University, Apple Inc.
Bio: Shakti Singh Chauhan is an academic researcher from General Electric. The author has contributed to research in topics: Heat transfer & Thermal resistance. The author has an hindex of 12, co-authored 43 publications receiving 385 citations. Previous affiliations of Shakti Singh Chauhan include Iowa State University & Apple Inc..
Papers
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20 May 2013TL;DR: A power overlay (POL) structure includes a POL sub-module as mentioned in this paper, which includes a dielectric layer and a semiconductor device having a top surface attached to the dielectrics layer.
Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.
50 citations
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26 Sep 2013TL;DR: In this paper, a package structure includes a dielectric layer, at least one semiconductor device attached to the layer, one or more sheet applied to the sheet and about the device to embed the semiconductor devices therein, and a plurality of vias formed to the semiconductors.
Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).
36 citations
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03 Mar 2015TL;DR: In this paper, a package structure includes a first dielectric layer, semiconductor devices attached to the first layer, and an embedding material applied to the embedding layer so as to embed the semiconductor device therein, with metal interconnects formed in the vias to form electrical interconnections.
Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.
32 citations
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21 Dec 2015TL;DR: In this article, a system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP.
Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.
21 citations
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TL;DR: In this paper, a residual electrical resistivity measurement is employed to study dislocation storage under tensile loading of freestanding electroplated Cu films (1-5μm grain size and 2-50μm thickness).
Abstract: Residual electrical resistivity measurement is employed to study dislocation storage under tensile loading of freestanding electroplated Cu films (1–5μm grain size and 2–50μm thickness). The results indicate that the nature of thickness effects (strengthening or weakening) depends on the underlying deformation mechanisms via the average grain size. A threshold grain size of about dg=5μm is identified to distinguish grain size effects in thicker films from those in thinner films. For dg>5μm, diminishing microstructural constraint with reduced thickness weakens the films due to dislocation annihilation near the free surface. For dg<5μm, reduction of film thickness leads to strengthening via grain boundary-source starvation.
19 citations
Cited by
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12 Jan 2017TL;DR: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface as mentioned in this paper, and a stiffener is disposed on the third surface.
Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
202 citations
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27 May 2015TL;DR: In this paper, a light-emitting device package including a lead frame formed of a metal and on which a light emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding is presented.
Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.
188 citations
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27 Mar 2017
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.
185 citations
01 Jan 1993
TL;DR: In this paper, the thermal behavior of arrays of micro heat pipes fabricated in silicon wafers was investigated using an infrared thermal imaging unit, the temperature gradients and maximum localized temperatures were measured and an effective thermal conductivity was computed.
Abstract: An experimental investigation was conducted to determine the thermal behavior of arrays of micro heat pipes fabricated in silicon wafers. Two types of micro heat pipe arrays were evaluated, one that utilized machined rectangular channels and the other that used an anisotropic etching process to produce triangular channels. Once fabricated, a clear pyrex cover plate was bonded to the top surface of each wafer using an ultraviolet bonding technique to form the micro heat pipe array. These micro heat pipe arrays were then evacuated and charged with a predetermined amount of methanol. Using an infrared thermal imaging unit, the temperature gradients and maximum localized temperatures were measured and an effective thermal conductivity was computed. The experimental results were compared with those obtained for a plain silicon wafer
146 citations
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14 Mar 2014TL;DR: In this article, a carrier substrate including an element region and a wiring region is constructed, and a metal wirings electrically connecting the electronic element and the wires are electrically connected on the first elastic layer.
Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
139 citations