S
Sheldon X.-D. Tan
Researcher at University of California, Riverside
Publications - 366
Citations - 4293
Sheldon X.-D. Tan is an academic researcher from University of California, Riverside. The author has contributed to research in topics: Speedup & Model order reduction. The author has an hindex of 29, co-authored 351 publications receiving 3717 citations. Previous affiliations of Sheldon X.-D. Tan include Fudan University & University of California, Berkeley.
Papers
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Proceedings ArticleDOI
Physics-based Electromigration Assessment for Power Grid Networks
TL;DR: A novel approach and techniques for physics-based electromigration (EM) assessment in power delivery networks of VLSI systems by replacing a currently employed conservative weakest segment criterion with an increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect segments.
Book
Advanced Model Order Reduction Techniques in VLSI Design
Sheldon X.-D. Tan,Lei He +1 more
TL;DR: This book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm.
Journal ArticleDOI
Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis
TL;DR: The improved formulation method is compared with traditional formulation methods, showing that the NA matrix is more compact and the generation of nonzero coefficients is reduced, since the CPU time and memory consumption is reduced when recursive determinant-expansion techniques are used to solve theNA matrix.
Journal ArticleDOI
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
TL;DR: Experimental results demonstrate that the proposed sequence-of-linear-program method is orders of magnitude faster than the best-known method based on conjugate gradients with constantly better solution qualities.
Proceedings ArticleDOI
Dynamic FPGA routing for just-in-time FPGA compilation
TL;DR: The concept of a standard hardware binary is introduced, using a just-in-time compiler to compile the hardware binary to an FPGA, and the Riverside On-Chip Router (ROCR) designed to efficiently route a hardware circuit for a simple configurable logic fabric is presented.