Shen-Li Chen

Bio: Shen-Li Chen is an academic researcher from National United University. The author has contributed to research in topics: Type (model theory). The author has an hindex of 2, co-authored 2 publications receiving 9 citations.

Strengthen Anti-ESD Characteristics in an HV LDMOS With Superjunction Structures

Abstract: In general, the antielectrostatic discharge (ESD) ability of a high voltage (HV) MOSFET device will be very low if it is not optimized through the addition of reliability engineering. Accordingly, in this paper, some embedded superjunction (SJ) device under tests (DUTs) of 45-V HV n-channel lateral-diffused MOS (nLDMOS) are developed, which offer a low on-resistance as compared with the traditional nLDMOS due to the redistribution of electric field or/and higher doping density in the drain side. In order to evaluate how various physical parameters affect the anti-ESD capability, these DUTs will change the widths and shapes of the P/N pillars. From the testing results, it can be found that the I t2 values of SJ-nLDMOS DUTs will be higher than that of a traditional nLDMOS, while the equivalent immunity level is even greater than HBM 10 kV. In this paper, the I t2 values of developed SJ-nLDMOS DUTs were increased at least by 109%, 31%, and 159% over that of the traditional nLDMOS for the Types 1-3 embedded SJ, respectively. Moreover, in some geometry architectures of an SJ-LDMOS, the holding voltage can be greater than the traditional nLDMOS. Therefore, by considering the relationships between these three kinds of SJ-nLDMOS DUTs and the I t2 values, it can be determined that the SJ structure is good for ESD/latch-up immunities especially for the ESD reliability.

Design and Layout Strategy in the 60-V Power pLDMOS With Drain-End Modulated Engineering of Reliability Considerations

Abstract: This study reports the impacts of various drain end layouts on the reliability and electrical performance of 60-V p-channel laterally diffused metal–oxide-semiconductor ( pLDMOS) FETs. For effectively improving the reliability, drain-end “N-P-N” and “P-N-P” permutated pLDMOSs embedded with silicon-controlled rectifiers (pLDMOS–SCRs) with discrete regulated structures in the drain strap were manufactured using a 0.25-μm BCD process. According to transmission-line pulse data, the $I_{t2}$ value is very low (only 0.644 A) for a pure pLDMOS transistor. However, embedding an SCR in the drain end results in a decrease in $V_{t1}$ , $V_{h}$ , and $V_{\rm BK}$ and increase in $I_{t2}$ values (>7 A), even for N-P-N and P-N-P drain-end arranged types. In addition, the $I_{t2}$ capability of the nonbutted-contact pLDMOS–SCR devices is satisfactory. By contrast, N-P-N and P-N-P stripe-type devices with the highest N+/P+ area ratio have less favorable electrical properties and lower anti-latchup (LU) immunity compared with a pure pLDMOS. In addition, the $V_{h}$ (and $V_{\rm BK}$ ) improvement of the P-N-P stripe type is more than 278% (and 23.7%) compared with the N-P-N stripe type. Therefore, pLDMOS–SCRs with a P-N-P stripe-type structure are a potential candidate for enhancing electrostatic discharge, LU immunities and electrical performance.

Nonlinear-Embedding Design Methodology Oriented to LDMOS Power Amplifiers

Abstract: In this paper, we apply for the first time the nonlinear-embedding technique to the design of power amplifiers (PAs) based on laterally-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors. Such a design technique is based on setting the transistor load line at the intrinsic current-generator plane, according to well-known theoretical guidelines. Then, the selected operating condition can be transposed at any design frequency at the extrinsic transistor terminals, by means of a model of the device nonidealities, such as the nonlinear intrinsic capacitances and the linear parasitic effects. A harmonically-tuned high-efficiency class-F and a wideband class-AB PAs operating within the FM broadcasting band 88 ÷ 108 MHz based on a 10-W LDMOS are then designed and realized. To definitely assess the validity of the proposed approach for the LDMOS technology, we compare the measured performance on the fabricated PAs with the expected predictions.

Robust lateral double-diffused MOS with interleaved bulk and source for high-voltage electrostatic discharge protection

Abstract: A device with bulk and source interleaved dotting is fabricated in a 0.5-µm 24 V CDMOS process, and the root cause of why it improves the multi-finger high-voltage lateral double-diffused MOS (LDMOS)’s electrostatic discharge (ESD) robustness is detected by Atlas three-dimensional device simulation and transmission line pulse system. Such device structure obtains strong ESD robustness by enlarging the intrinsic base resistance without increasing device area and sacrificing any ESD performance of nLDMOS. The measurement results demonstrated that, compared with traditional gate-grounded nLDMOS (GG-nLDMOS) with a total length of 400 μm, the proposed device can effectively raise the secondary breakdown current (I t2) from 2.43 A up to 5.55 A, and enhance the ESD current discharge efficiency from 0.29 to 0.70 mA/μm2.

ESD failure analysis and robustness improvement for multi-STI-finger LDMOS used as output device

Abstract: The MSF-LDMOS will suffer from high ESD failure risk when used as output device. In this work, it is found that the different ratios of STI width to silicon width have impact not only on breakdown voltage and R dson, sp , but also on ESD robustness. Thus, the ESD failure mechanism of MSF-LDMOS is comprehensively investigated. Furthermore, a novel structure with multiple stair-STI fingers is proposed by alleviating the crowded current density. For the novel MSSF-LDMOS, the ESD robustness increases by 10% and the R dson, sp decreases by 2.5% with only 1.2% reduction of breakdown voltage comparing with the conventional MSF-LDMOS.

Signal Control Switching for Improving Large Array Devices' ESD Performances

Abstract: Electrostatic Discharge (ESD) performance of large array device (LAD) is a big challenge since the common ESD skill cannot be used. A novel signal control switching (SCS) architecture for adding LAD's ESD robustness is proposed in this paper. A little layout area is increased, but a huge ESD robustness increase can be obtained.

Robust reliability and electrical performances by the bulk-contact modulation in 60-V p-channel LDMOS power components

Abstract: To increase reliability and electrical performance, shallow-trench isolation (STI) (or called field-oxide (FOX)) structures were inserted in the bulk-contact region of 60-V high-voltage p-channel l...