Here we have simulated the influence on the characteristics of Silicon Nanowire Junction-less transistor (JLT) with help of PADRE MuGFET simulation tools in the situation when we vary the length of gate. We noticed that when welength of gate was changed, the corresponding characteristics changed in accordance with it. We have examined this change by analyzing different output parameters which includes its transfer characteristics, transconductance, Drain Induced Barrier Lowering (DIBL) effect, electric potential, the value of threshold voltage and electric field of the device. We have results which shows that when we increase the length of gate, the value of the current decrease keeping gat voltage (Vg) at 0V. The value range of parameters like electric potential and electric field increased while there was a drop in threshold voltage. The peak of transconductance started reaching new heights but the observations in DIBL effect was just opposite. From the simulations we got to know that use of devices with smaller length of gates should be preferable as the results were better with them.

Gate Length Modulation of Junction-less Transistor Based on Silicon Nanowire

Dual-gated silicon nanowire (SiNW) field-effect transistors (FETs) have been fabricated by using electron-beam lithography. SiNW devices (W ≈ 60 nm) exhibit an on/off current ratio greater than 106, which is more than 3 orders of magnitude higher than that of control devices prepared simultaneously having a large channel width (∼5 μm). In addition, by changing the local energy-band profile of the SiNW channel, the top gate is found to suppress ambipolar conduction effectively, which is one of the factors limiting the use of nanotube or nanowire FETs for complimentary logic applications. Two-dimensional numerical simulations show that the gate-induced electrostatic control is improved as the channel width of the FETs decreases. Therefore, enhanced channel modulations can be achieved in these dual-gated SiNW devices.

/pdf/enhanced-channel-modulation-in-dual-gated-silicon-nanowire-5bd29woyyd.pdf

Enhanced Channel Modulation in Dual-Gated Silicon Nanowire Transistors

This research work uses sp3d5s* tight-binding models to design and analyze the structural properties of group IV and III-V oriented, rectangular Silicon (Si) and Gallium Arsenide (GaAs) Nanowires (NWs). The electrical characteristics of the NWs, which are shielded with Lanthanum Oxide (La2O3) material and the orientation with z [001] using the Non-Equilibrium Green Function (NEGF) method, have been analyzed. The electrical characteristics and the parameters for the multi-gate nanowires have been realized. A nanowire comprises a heavily doped n+ donor source and drains doping and n-donor doping at the channel. The specified nanowire has a gate length and channel length of 15 nm each, a source-drain device length LSD = 35 nm, with La2O3 as 1 nm (gate dielectric oxide) each on the top and bottom of the core material (Si/GaAs). The Gate-All-Around (GAA) Si NW is superior with a high (ION/IOFF ratio) of 1.06 × 109, and a low leakage current, or OFF current (IOFF), of 3.84 × 10−14 A. The measured values of the mid-channel conduction band energy (Ec) and charge carrier density (ρ) at VG = VD = 0.5 V are −0.309 eV and 6.24 × 1023 C/cm3, respectively. The nanowires with hydrostatic strain have been determined by electrostatic integrity and increased mobility, making them a leading solution for upcoming technological nodes. The transverse dimensions of the rectangular nanowires with similar energy levels are realized and comparisons between Si and GaAs NWs have been performed.

/pdf/design-and-analysis-of-gallium-arsenide-based-nanowire-using-2b4e45zk.pdf

Design and Analysis of Gallium Arsenide-Based Nanowire Using Coupled Non-Equilibrium Green Function for RF Hybrid Applications

This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.

Shenbagavalli A

Papers

Drain current characteristics of silicon nanowire field effect transistor