This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

integrations and challenges of novel high-k gate stacks in advanced cmos technology

A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (KVCO), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is - 87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm2.

A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip

The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130 nm, 90 nm, and 65 nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle. It is shown that the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET. Experimental and simulation results are presented for mixed MOSFET/TFET circuits. The usage of the TFET does not cause delay degradation. The static power consumption and signal integrity are improved compared to the CMOS realization.

Scaling properties of the tunneling field effect transistor (TFET) : Device and circuit

In this work, we implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver using various low-power techniques for low-rate wireless personal area network (IEEE 802.15.4 LR_WPAN) applications in 0.18-μm CMOS technology. In order to achieve an ultra low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are all implemented in this transceiver. The transmitter achieves less than 5.0% error vector magnitude (EVM) at 5 dBm output, and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is below 14.3 mA for the data receiving mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V power supply. That is considered to be lowest for the 2.4 GHz CMOS ZigBee transceiver compared to open literature results.

An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 mum CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78-5.19 GHz and 12.19-12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are -117.16 dBc/Hz and -112.15 dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

This letter proposes 5-GHz low power differential Armstrong voltage controlled oscillators (VCOs) based on balanced topology. One designed VCO uses two single-ended Armstrong VCOs coupled to each other in parallel by balanced structure. The other current-reused VCO uses two single-ended Armstrong VCOs stacked in series. The former VCO oscillates from 4.96 to 5.34GHz and the power consumption is 3.9mW at 0.6-V supply voltage. The latter operates from 4.98 to 5.45GHz and dissipates 2.59mW at 1.8-V supply voltage. The measured phase noises are about -116.71dBc/Hz and -110.02dBc/Hz at 1-MHz offset frequency from 5.1-GHz band, respectively. The former and the latter VCO have an advantage of low power consumption and provide a good figure of merit of about -185dBc/Hz and -180dBc/Hz, respectively

5-GHz Low Power Current-Reused Balanced CMOS Differential Armstrong VCOs

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW

Low-Phase Noise Hartley Differential CMOS Voltage Controlled Oscillator

A 1.1-GHz voltage control oscillator (VCO) using a standard 0.18-mum CMOS 1P6M process is fabricated. The VCO was designed with dynamic threshold voltage metal-oxide-semiconductor field-effect transistors and extremely-low-voltage and low power operation is achieved using on-chip transformers in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. This VCO prototype is designed for a 0.34-V supply voltage while the output phase noise is -121.2dBc/Hz at 1-MHz offset frequency at the carrier frequency of 1.14GHz, the figure of merit is -192.0dB. The total power consumption is 103.7muW with the 0.34-V supply voltage. Tuning range is from 1.06 to 1.14GHz about 80MHz while the control voltage was tuned from 0 to 1.8V. The die area is 0.625times0.79mm2

A Low Voltage and Power $LC$ VCO Implemented With Dynamic Threshold Voltage MOSFETS

This letter proposes a wide-locking range divide-by-3 injection-locked frequency divider fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an nMOS cross-coupled p-core Armstrong LC oscillator and a center-tapped inductor in series with the pMOSFETs. The pMOSFETs are used as a linear and second harmonic mixer. At the supply voltage of 1 V, the free-running frequency is from 7.84 to 8.42 GHz, the current and power consumption of the divider without buffers are 4 mA and 4 mW respectively. At the incident power of 0 dBm, the locking range is 4.28 GHz (19.8%), from the incident frequency 19.52 to 23.8 GHz.

Sheng-Lyang Jang

Papers

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

5-GHz Low Power Current-Reused Balanced CMOS Differential Armstrong VCOs

Low-Phase Noise Hartley Differential CMOS Voltage Controlled Oscillator

A Low Voltage and Power $LC$ VCO Implemented With Dynamic Threshold Voltage MOSFETS

A 90 nm CMOS LC-Tank Divide-by-3 Injection-Locked Frequency Divider With Record Locking Range