A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long Instruction Word Controlling Plural Independent Processor Operations

Several modifications to the CORDIC method of computing angles and performing rotations are presented: (1) the use of redundant (carry-free) addition instead of a conventional (carry-propagate) one; (2) a representation of angles in a decomposed form to reduce area and communication bandwidth; (3) the use of on-line addition (left-to-right, digit-serial addition) to replace shifters by delays; and (4) the use of online multiplication, square root, and division to compute scaling factors and perform the scaling operations. The modifications improve the speed and the area of CORDIC implementations. The proposed scheme uses efficiently floating-point representations. The application of the modified CORDIC method to matrix triangularization by Givens' rotations and to the computation of the singular value decomposition (SVD) are discussed. >

Redundant and on-line CORDIC: application to matrix triangularization and SVD

A structure for routing connections in a semiconductor circuit constructed on a silicon wafer substrate, and a method for making that structure. The routing structure is constructed using two layers of electrical conductors and a set of interlayer connectors, but one of the electrical connection layers is predetermined and need not be programmable. The fixed electrical connection layer is laid out with a plurality of preselected routing connections, such as a set of horizontal or "east-west" connections laid out in a predetermined pattern. The variable electrical connection layer is programmed to make use of the preselected routing connections to connect disparate locations within the circuit on the semiconductor wafer, such as by making vertical or "north-south", and also horizontal, connections to selected horizontal connectors. The pattern of horizontal connections comprises a plurality of horizontal lines, with vertical spacing between pairs of neighboring lines. Each line comprises a set of one or more horizontal segments, with each segment extending for a selected length, and with selected amounts of horizontal spacing between pairs of neighboring segments. Selected lines, such as those coupled to ground or power, may continue without breaks. Preferably, the spacing between lines, the length of each segment, and the spacing between segments are all preselected before construction of the semiconductor circuit.

Circuit routing structure using fewer variable masks

This paper describes new methods for producing optimal binary signed-digit representations. This can be useful in the fast computation of exponentiations. Contrary to existing algorithms, the digits are scanned from left to right (i.e., from the most significant position to the least significant position). This may lead to better performances in both hardware and software.

Optimal left-to-right binary signed-digit recoding

A method for manufacturing a semiconductor device includes a step, after forming a polycrystalline silicon layer, of doping oxygen and/or nitrogen by ion implantation in a predetermined portion of the polycrystalline silicon layer and converting the predetermined portion into a resistive element. The polycrystalline silicon layer is formed to cover a contact hole which exposes a predetermined portion of a conductive region, that is, a doped or semiconductor region or a wiring layer formed in contact with a semiconductor body. Within this contact hole and within the region of the polycrystalline silicon layer which is in contact with the doped region or the wiring layer, the polycrystalline silicon layer is converted into the resistive element by ion implantation.

Method for manufacturing a semiconductor device

A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.

Design of high speed MOS multiplier and divider using redundant binary representation

An arithmetic processor and an addition/subtraction circuit therefor are disclosed. The arithmetic processor comprises a plurality of the addition/subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) with respect to respective digits of two operands. An addition/subtraction unit comprises a first circuit and a second circuit coupled to receive binary signals each representing a respective digit of the operands. At least a first of the two binary signals is a 2-bit signal representing a signed digit expression, one bit of which ("the sign bit") represents the sign of one of the digits of the operands and the other bit of which ("the magnitude bit") represents the magnitude of that one digit of the operands. The first circuit provides a binary signal representing an intermediate carry (or borrow) and the second circuit provides a binary signal representing an intermediate sum (or difference) from the two binary signals representing the digits of the operands. The addition/subtraction unit further comprises a third circuit which is coupled to receive the intermediate sum (or difference) binary signal output from the second circuit and a binary signal representing an intermediate carry (or borrow) from a next-lower-order digit, and outputs a 2-bit binary signal representing an addend (or subtrahend). That 2-bit signal output by the third circuit represents a signed digit expression, one bit, i.e., the sign bit, represents the sign of the addend (or subtrahend) and the other bit, i.e., the magnitude bit, represents the magnitude of the addend (or subtrahend).

Arithmetic processor and multiplier using redundant signed digit arithmetic

An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.

High speed multiplier utilizing signed-digit and carry-save operands

High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor

In a C MOS IC as shown in FIG. 7(A) and FIG. 8, the IC comprises vertical row of horizontally long blocks, each block comprising p-type MOS transistor region and n-type MOS transistor region, the IC comprises horizontal wirings of aluminum (31, 32, 33) and vertical wirings of polycrystalline silicon (61, 62, 63, 64, 65, 41, 42), with insulation films on the upper side and on the lower side of the polycrystalline silicon film, between the rows (I, II, . . .), said horizontal aluminum wirings (31, 32, 33) and said polycrystalline silicon wiring (61, 62 . . ., 41, 42) being appropriately connected through openings (105, 105 . . .) formed in said insulation film inbetween, said vertical polycrystalline silicon wirings being connected through aluminum wirings in said blocks.

Shigeo Kuninobu

Papers

Design of high speed MOS multiplier and divider using redundant binary representation

Arithmetic processor and multiplier using redundant signed digit arithmetic

High speed multiplier utilizing signed-digit and carry-save operands

High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor

C MOS IC and method of making the same