Statistical analysis of SRAM has emerged as a challenging issue because the failure rate of SRAM cells is extremely small. In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells. In particular, we adapt the Gibbs sampling technique from the statistics community to find the optimal probability distribution for importance sampling with a low computational cost (i.e., a small number of transistor-level simulations). The proposed Gibbs sampling method applies an integrated optimization engine to adaptively explore the failure region in a Cartesian or spherical coordinate system by sampling a sequence of 1-D probability distributions. Several implementation issues such as 1-D random sampling and starting point selection are carefully studied to make the Gibbs sampling method efficient and accurate for SRAM failure rate prediction. Our experimental results of a 90 nm SRAM cell demonstrate that the proposed Gibbs sampling method achieves 1.4-4.9× runtime speedup over other state-of-the-art techniques when a high prediction accuracy is required (e.g., the relative error defined by the 99% confidence interval reaches 5%). In addition, we further demonstrate an important example for which the proposed Gibbs sampling algorithm accurately estimates the correct failure probability, while the traditional techniques fail to work.

/pdf/efficient-sram-failure-rate-prediction-via-gibbs-sampling-heybb2k0xf.pdf

Efficient SRAM Failure Rate Prediction via Gibbs Sampling

Statistical analysis of SRAM has emerged as a challenging issue because the failure rate of SRAM cells is extremely small. In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells. In particular, we adapt the Gibbs sampling technique from the statistics community to find the optimal probability distribution for importance sampling with minimum computational cost (i.e., a small number of transistor-level simulations). The proposed Gibbs sampling method applies an integrated optimization engine to adaptively explore the failure region by sampling a sequence of one-dimensional probability distributions. Several implementation issues such as one-dimensional random sampling and starting point selection are carefully studied to make the Gibbs sampling method efficient and accurate for SRAM failure rate prediction. Our experimental results of a commercial 65nm SRAM cell demonstrate that the proposed Gibbs sampling method achieves 3~10x runtime speed-up over other state-of-the-art techniques without surrendering any accuracy.

/pdf/efficient-sram-failure-rate-prediction-via-gibbs-sampling-4cj18dzfsn.pdf

Efficient SRAM failure rate prediction via Gibbs sampling

This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-trigger inverter write assist technique that controls the trip voltage of the Schmitt-trigger inverter. The proposed Schmitt-trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang's 10T, the Schmitt-trigger-based 10T, and MH's 9T static random access memory cells, respectively, based on 22-nm FinFET technology.

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., static random-access memory, D flip-flop, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum.” Our proposed SSS method can simultaneously estimate the rare failure rates for multiple performances and/or specifications with only a single set of transistor-level simulations. To quantitatively assess the accuracy of SSS, we estimate the confidence interval of SSS based on bootstrap. Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves significantly better accuracy than the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.

/pdf/fast-statistical-analysis-of-rare-circuit-failure-events-via-2venkabams.pdf

Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space

This brief presents a review of developments in spin-transfer-torque magnetoresistive random access memory (STT-MRAM) sensing over the past 20 years from a circuit design perspective. Various sensing schemes are categorized and described according to the data-cell variation-tolerant characteristics, pre-amplifiers, and offset tolerance. Key breakthroughs for achieving the optimal reference scheme, read disturbance prevention, read energy reduction, accurate yield estimation, and overcoming other non-idealities are discussed. This review is intended to facilitate further enhancement of STT-MRAM sensing in advanced technology nodes, thereby fulfilling STT-MRAM’s potential as a universal memory.

STT-MRAM Sensing: A Review

In this paper, a significant acceleration of estimating low-failure rate in a high-dimensional SRAM yield analysis is achieved using sequential importance sampling. The proposed method systematically, autonomously, and adaptively explores failure region of interest, whereas all previous works needed to resort to brute-force search. Elimination of brute-force search and adaptive trial distribution significantly improves the efficiency of failure-rate estimation of hitherto unsolved high-dimensional cases wherein a lot of variation sources including threshold voltages, channel-length, carrier mobility, etc. are simultaneously considered. The proposed method is applicable to wide range of Monte Carlo simulation analyses dealing with high-dimensional problem of rare events. In SRAM yield estimation example, we achieved 106 times acceleration compared to a standard Monte Carlo simulation for a failure probability of 3 × 10−9 in a six-dimensional problem. The example of 24-dimensional analysis on which other methods are ineffective is also presented.

Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis

Monte Carlo simulations have been widely adopted for analyzing circuit properties, such as SRAM yield, under strong influence of process variations. Enormous calculation time is required in such a simulation due to the low defect probabilities. In this paper, we propose a robust shift-vector determination for mean-shift importance sampling, by which efficiency and stability of the Monte Carlo simulation is improved. In the proposed method, the hypersphere sampling is developed to autonomously find the optimal shift-vector. The sampling is also limited to the regions where meaningful contribution to the yield is recognized. Simulation examples reveal that the proposed technique stably and efficiently estimates yield of noise stabilities of an SRAM cell. At the failure probability of 10−10, the number of calculation trials has been reduced by six orders magnitude compared with a conventional Monte Carlo simulation.

Robust importance sampling for efficient SRAM yield analysis

A MOS transistor-array structure and an accurate measurement procedure of subthreshold leakage current variation is proposed. New contributions consist of two architectural improvements called LCS and PES, and measured data treatment called MCC. The LCS, leakage current cutoff switch, reduces unwanted leakage current of the non-target devices which masks the target leakage current. The PES, potential equalizing supply, further reduces masking current to an atto ampere order by setting source and drain terminals of the LCS equal. The MCC, masking current cancellation, improves measurement accuracy by subtracting remaining masking current. The proposed array structure and the procedure virtually eliminate usual constraint on the number of transistors that can be present in an array. The array structure also offers greater flexibility in choosing a row-column aspect ratio and allows different types of MOS transistors to be interweaved. Simulation study proved effectiveness of the proposed architecture showing well over a million of devices to be measurable with less than 1 % error

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation

A procedure called box-scan search which identifies possible weakness in a power distribution network of an LSI is proposed. In the procedure, node pairs having large voltage difference but located in close proximity are considered as good candidates for improving connections using additional wire. The virtual box is the grid space in which the node voltages are compared. Scans of node voltages of the virtual box generate a prioritized list of the fixing point candidate. Experimental results show effectiveness of the proposed procedure for pointing out the node pairs which requires low-impedance connection.

Weakness identification for effective repair of power distribution network

A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.

/pdf/linear-time-calculation-of-on-chip-power-distribution-2otym3wy0m.pdf

Shiho Hagiwara

Papers

Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis

Robust importance sampling for efficient SRAM yield analysis

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation

Weakness identification for effective repair of power distribution network

Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence