다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Based on 3D simulations, we report a performance assessment of triple- and double-gate FinFETs for high performance (HP), low operating power (LOP) and low standby power (LSTP) logic technologies according to ITRS 65 nm node specifications. The impact of spacer width, lateral source/drain doping gradient, aspect ratio, fin thickness and height along with gate work function on the device performance has been analysed in detail and guidelines are presented to meet the ITRS projections. The design guidelines proposed for a 65 nm node are also examined for a 45 nm node for triple- and double-gate FinFETs. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimized to achieve low values of intrinsic delay. FinFETs should be designed with a higher aspect ratio (~4) along with lower values of fin thickness to achieve ITRS targets for off-current and intrinsic delay. Triple-gate FinFETs show greater design flexibility in selecting important technological and device parameters as compared to double-gate devices. A design window is presented to achieve ITRS targets for the three logic technology requirements with triple- and double-gate FinFETs.

https://iopscience.iop.org/article/10.1088/0268-1242/21/4/002/pdf

Performance assessment of nanoscale double- and triple-gate FinFETs

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient ( d ), (ii) spacer width ( s ), (iii) spacer to doping gradient ratio ( s / d ) and (iv) silicon film thickness ( T si ), on short channel effects – threshold voltage ( V th ) and subthreshold slope ( S ), on-current ( I on ), off-current ( I off ) and I on / I off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG SOI devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs : Analytical model and design considerations

Wet chemical cleaning is central to semiconductor device processing. For InP-based optoelectronic devices, controlling wet processing is challenging because of the high reactivity of InP surfaces in ambient air. In situ techniques are therefore critical to monitor and understand wet chemical etching and oxidation. We have combined in situ and ex situ Fourier transform infrared absorption spectroscopy, in direct transmission and multiple internal reflection configurations, with ex situ x-ray photoelectron spectroscopy to investigate the wet-chemical removal of “epi-ready” oxides on InP(100). Even dilute solutions of HCl, HF, or H2SO4 are found to completely remove the epi-ready oxides. For both HCl and HF, the InP surface is left unpassivated, exhibiting rapid recontamination and reoxidation upon air exposure. In contrast, H2SO4 aggressively etches the surface, and forms a thick and fragile oxide cap that can be washed away during a subsequent water rinse. This systematic in situ vibrational study of InP oxide chemistry provides a basis for a mechanistic understanding of wet chemical etching and oxidation.

Wet chemical cleaning of InP surfaces investigated by in situ and ex situ infrared spectroscopy

The pseudo-MOS transistor (Psi-MOSFET characteristics) is a simple and successful technique for the monitoring of silicon-on-insulator (SOI) wafer quality. To characterize modern ultrathin films, a reconsideration and review of Psi-MOSFET physics and models is required. Selected numerical simulations are presented, which shed light on the intriguing features governing Psi-MOSFET characteristics. Updated models accounting for the density of interface states and channel-to-surface coupling effects in ultrathin SOI wafers with passivated and nonpassivated surfaces are derived. These analytical models show excellent agreement with measurement and simulation data.

Revisited Pseudo-MOSFET Models for the Characterization of Ultrathin SOI Wafers

The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility.

Detailed investigation of geometrical factor for pseudo-MOS transistor technique

This paper discusses the importance of controlling the lateral diffusion of impurities around the source and drain (S/D) junctions in sub-100-nm channel single-gate silicon-on-insulator (SOI) MOSFETs. Since any reduction in lateral diffusion length must consider the tradeoff between drivability and short-channel effect with regard to the threshold voltage, optimization of lateral diffusion length is essential in the device design stage. We note that the net performance improvement offered by device-scaling is quite limited, even if lateral diffusion length is optimized in some way. It seems obvious that high-/spl kappa/ materials are needed in order to improve net device performance in the sub-100-nm technology regime. In addition, with regard to the impact of the thermal budget on lateral diffusion control, new doping materials such as Sb and In, will be required in the near future. In the case of nMOSFET, however, advanced structures, such as an elevated layer, and advanced annealing process are needed to provide enhanced control of S/D diffusion regions.

Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs

This paper simulates the transport characteristics of ultrathin silicon-on-insulator MOSFETs, and evaluates the influence of the quantum-mechanical mechanism on the short-channel effects on the basis of the density-gradient model. It is clearly shown that the quantum-mechanical mechanism suppresses the buried-insulator-induced barrier lowering with regard to the subthreshold swing because the surface dark space yields a high-field region in the source region adjacent to the channel. It is also suggested that the quantum-mechanical mechanism enhances the impact of the apparent charge-sharing effect on the threshold voltage because the surface dark space effectively increases the thickness of the gate-oxide layer and buried-oxide layer.

Quantum-mechanical suppression and enhancement of SCEs in ultrathin SOI MOSFETs

The paper describes the impact of pseudo-MOS technique on threshold and flatband voltages, and why the threshold and flatband voltages depend on silicon-on-insulator (SOI) layer thickness. Our measurements and simulations suggest that the band-offset-induced depletion beneath the source contact obstructs the local formation of the inversion layer at the SOI/buried oxide interface; this effect becomes significant when the SOI layer thickness is reduced. The SOI layer thickness dependence of flatband voltage is analyzed in a similar manner. The temperature dependence of threshold and flatband voltages is also addressed.

Possible influence of the Schottky contacts on the characteristics of ultrathin SOI pseudo-MOS transistors

This paper discusses the role of trap-assisted-tunneling process in controlling the ON- and OFF-state current levels and its impacts on the current-voltage characteristics of a tunnel field-effect transistor. Significant impacts of high-density traps in the source region are observed that are discussed in detail. With regard to recent studies on isoelectronic traps, it has been discovered that deep level density must be minimized to suppress the OFF-state leakage current, as is well known, whereas shallow levels can be utilized to control the ON-state current level. A possible mechanism is discussed based on simulation results.

Shingo Sato

Papers

Detailed investigation of geometrical factor for pseudo-MOS transistor technique

Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs

Quantum-mechanical suppression and enhancement of SCEs in ultrathin SOI MOSFETs

Possible influence of the Schottky contacts on the characteristics of ultrathin SOI pseudo-MOS transistors

Revisiting the role of trap-assisted-tunneling process on current-voltage characteristics in tunnel field-effect transistors