Shinichi Kouda

Bio: Shinichi Kouda is an academic researcher from Tokyo University of Agriculture and Technology. The author has contributed to research in topics: Graph (abstract data type) & Topology (electrical circuits). The author has an hindex of 1, co-authored 1 publications receiving 24 citations.

Improved method of cell placement with symmetry constraints for analog IC layout design

Abstract: Recently, it is often required in high performance analog IC design that some cells are placed symmetrically to horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair, but this method has the following defects: (1) Some cells overlap each other. (2) The closest cell placement satisfying both the symmetry and topology constraints may not be obtained. (3) How to place cells symmetrically is mentioned only for one axis and there is no explanation for plural axes. In this paper, we propose an efficient method to obtain the closest cell placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair using linear programming. The proposed method obtains a simple constraint graph from a sequence-pair and derives a set of linear constraint expressions from the graph. The number of linear expressions decreases by substituting the expressions for dependent variables. Then the solutions are obtained by linear programming. The effectiveness of the proposed method was shown by computational experiments.

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

Abstract: In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions

Abstract: The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.

Analog placement with symmetry and other placement constraints

Abstract: In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. Instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. The maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. We have compared our method with the most updated results on this problem [2] when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. We will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising.

Analog placement based on novel symmetry-island formulation

Abstract: In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only ID symmetry constraints, our ASF-B*-tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*- tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.

Analog placement with common centroid and 1-D symmetry constraints

Abstract: In this paper, we will present a placement method for analog circuits. We consider both common centroid and 1-D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair representation that can cover completely the set of all placements satisfying the common centroid and 1-D symmetry constraints. This condition is essential for a good searching process to solve the problem effectively. Symmetric placement is an important step to achieve matchings of other electrical properties like delay and temperature variation. We have compared our results with those presented in the most updated previous works. Significant improvements can be obtained by our approach in both common centroid and 1-D symmetry placements, and we are the first who can handle both constraints simultaneously.