Shivam Priyadarshi

Bio: Shivam Priyadarshi is an academic researcher from Qualcomm. The author has contributed to research in topics: Cache & Central processing unit. The author has an hindex of 8, co-authored 33 publications receiving 313 citations. Previous affiliations of Shivam Priyadarshi include North Carolina State University.

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring

Abstract: The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.

A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

Abstract: A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simulations are compared to measurements for a token-generating asynchronous 3DIC clocking at a maximum frequency of 1 GHz. The electrical network is based on computationally efficient electrothermal macromodels of standard and custom cells. These are linked in a physically consistent manner with a detailed thermal network extracted from an OpenAccess layout file. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.

Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things

Abstract: In this article, we present Catena, a near-threshold voltage 16-core programmable spatial array accelerator supporting workloads for ultralow-power (ULP) mobile and embedded Internet of Things applications. We observe that employing supply voltage scaling alone in a large-scale, massively parallel spatial architecture, such as Catena, results in marginal runtime energy efficiency. The reason is that ultralow-voltage operation magnifies the energy waste of underutilized and always-on hardware in portion to the system’s total energy consumption. Hence, we propose circuit and architecture techniques to minimize such energy waste and extend the energy efficiency of our spatial array accelerator architecture. To demonstrate the effectiveness of the proposed techniques, we design and prototype Catena in a 65-nm low-power CMOS. Our prototype achieves 228 pJ/cycle. As compared to a spatial-like architecture running the same workload, Catena achieves 2.7 $\times $ higher energy efficiency.

Pathfinder 3D: A flow for system-level design space exploration

Abstract: Three dimensional integration technology has the potential to provide enhanced performance and device density gains beyond that available from technology scaling alone. However, it provides plethora of design choices for system designers. The full exploitation of the benefits of 3D integration requires a system-level exploration flow which can facilitate in finding an optimal 3D design by comparing possible early design choices. In this paper we present a flow for fast system-level exploration useful for path finding studies. The flow enables users to explore the tradeoff between different stacking and partitioning schemes in terms of performance, power, and temperature. We also present a free open source design kit compiler, FreePDK3D45 and a tool for fast floorplan evaluation of TSV-based digital architectures, Pathfinder3D. The open source design kit and architecture evaluator can help the community to research, learn and explore the various aspects of 3D integration. Using the proposed flow and design kit, we present a case study of 3D integration of a Network on Chip. This case study demonstrates system-level comparisons of the performance, power and temperature of different homogenously partitioned stacking schemes.

Method and apparatus for coupling an antenna to a device

Abstract: Aspects of the subject disclosure may include, for example, receiving, by a feed point of a dielectric antenna, electromagnetic waves from a dielectric core coupled to the feed point without an electrical return path, where at least a portion of the dielectric antenna comprises a conductive surface, directing, by the feed point, the electromagnetic waves to a proximal portion of the dielectric antenna, and radiating, via an aperture of the dielectric antenna, a wireless signal responsive to the electromagnetic waves being received at the aperture. Other embodiments are disclosed.

Backhaul link for distributed antenna system

Abstract: A distributed antenna and backhaul system provide network connectivity for a small cell deployment. Rather than building new structures, and installing additional fiber and cable, embodiments described herein disclose using high-bandwidth, millimeter-wave communications and existing power line infrastructure. Above ground backhaul connections via power lines and line-of-sight millimeter-wave band signals as well as underground backhaul connections via buried electrical conduits can provide connectivity to the distributed base stations. An overhead millimeter-wave system can also be used to provide backhaul connectivity. Modules can be placed onto existing infrastructure, such as streetlights and utility poles, and the modules can contain base stations and antennas to transmit the millimeter-waves to and from other modules.

Remote distributed antenna system

Abstract: A distributed antenna system is provided that frequency shifts the output of one or more microcells to a 60 GHz or higher frequency range for transmission to a set of distributed antennas. The cellular band outputs of these microcell base station devices are used to modulate a 60 GHz (or higher) carrier wave, yielding a group of subcarriers on the 60 GHz carrier wave. This group will then be transmitted in the air via analog microwave RF unit, after which it can be repeated or radiated to the surrounding area. The repeaters amplify the signal and resend it on the air again toward the next repeater. In places where a microcell is required, the 60 GHz signal is shifted in frequency back to its original frequency (e.g., the 1.9 GHz cellular band) and radiated locally to nearby mobile devices.

Guided-wave transmission device with non-fundamental mode propagation and methods for use therewith

Abstract: Aspects of the subject disclosure may include, for example, a transmission device that includes a transmitter that generates a first electromagnetic wave to convey data. A coupler couples the first electromagnetic wave to a single wire transmission medium having an outer surface, to forming a second electromagnetic wave that is guided to propagate along the outer surface of the single wire transmission medium via at least one guided wave mode that includes an asymmetric or non-fundamental mode having a lower cutoff frequency. A carrier frequency of the second electromagnetic wave is selected to be within a limited range of the lower cutoff frequency, so that a majority of the electric field is concentrated within a distance from the outer surface that is less than half the largest cross sectional dimension of the single wire transmission medium, and/or to reduce propagation loss. Other embodiments are disclosed.