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Shivani Maurya

Bio: Shivani Maurya is an academic researcher from International Institute of Information Technology, Hyderabad. The author has contributed to research in topics: Multiplier (economics) & Computer science. The author has an hindex of 1, co-authored 1 publications receiving 4 citations.

Papers
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Proceedings ArticleDOI
01 Nov 2015
TL;DR: An architecture for an approximate multiplier, accuracy of which can be configured during the run-time, which is successfully used in a JPEG conversion application and performances of different accuracy modes are compared.
Abstract: Real-time multimedia applications which demand very low decoding delays are increasing day-by-day. To address this challenge, in error-resilient applications, many approximate computing architectures for delay critical units have been proposed. In this paper, we propose an architecture for an approximate multiplier, accuracy of which can be configured during the run-time. According to the requirement of the application, the multiplier can be configured to operate in an exact mode or in any of the approximate modes, reducing its decoding delay and the dynamic power consumed. The architecture for the proposed approximate multiplier has been synthesized and simulated using Cadence design tools. Using 16-bit multiplication, it has been demonstrated that, the pass-rate and the propagation delay of the proposed multiplier is comparable or better than most of the published inaccurate multipliers. The proposed approximate multiplier is successfully used in a JPEG conversion application and performances of different accuracy modes are compared.

6 citations

Proceedings ArticleDOI
01 Jul 2022
TL;DR: This paper proposes an hardware implementation of HCD that relies on approximating the intermediate multiplication operations using Dynamic Range Unbiased Multiplier (DRUM), and explores how the errors due to approximate operations propagate to the corner response and attempts to find a threshold that adapts to this inaccuracy across images.
Abstract: Image processing algorithms with intrinsic robustness to errors can be approximated for significant resource and energy savings while still meeting the end-user requirements. FPGA-based implementations can increase their suitability for real-time high-speed multimedia applications by leveraging Approximate Computing, an independent field that explores methods to reduce computation costs by allowing minor degradation in intermediate computations. With high volume of pixel level computations, corner detection algorithms such as the Harris Corner Detector (HCD), offer wide range of targets for such strategies. In this paper, we propose an hardware implementation of HCD that relies on approximating the intermediate multiplication operations using Dynamic Range Unbiased Multiplier (DRUM). With run-time configurable bit-width control of DRUM instances, the visual quality of outputs is shown to depend on the varying accuracy of the corner response. We explore how the errors due to approximate operations propagate to the corner response and attempt to find a threshold that adapts to this inaccuracy across images. The experimental results for implementations on Virtex-7 and Zynq-7000 FPGA devices show that our approximate architecture can match the performance of other HCD implementations while hardly utilizing any on-board memory and signal processing resources. Synthesis results show that the proposed implementation achieves over 60% increase in maximum frequency compared to the base implementation. Finally, the quality metric analysis facilitates the selection of approximate configuration suited to the needs of an application.

Cited by
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Book ChapterDOI
01 Jan 2021
TL;DR: In this paper, the authors present the development of the approximate multiplier (AMP) architectures design and evolution as well as present research areas in AMP. This systematic study includes the new architectures used by researchers to improve the design of AMP and the advantages over other methods in this paper.
Abstract: Recently Low Power (LP) and High Speed (HS) of real-time computing is necessary for various application areas like image processing, neural network, internet of things and Digital Signal Processing (DSP). 86% of the data processing time in a real-time 3-D graphics system is due to DIVision (DIV) operation, and MULtiplier (MUL) OPeration (OP). Approximate MultiPlier (AMP) is the possible key for hardware efficient and fast MUL OP. In the last 10 years, the APP multiplier becomes a main arithmetic component for many applications. However, development in systematic approach along with the merits and demerits is not relived in the literature survey. Hence this paper not only presents about the development of the AMP architectures design and evolution but also presents research areas in AMP. This systematic study includes the new architectures used by researchers to improve the design of AMP and the advantages over other methods in respect of AMP are also highlighted.

6 citations

Proceedings ArticleDOI
23 Jul 2020
TL;DR: This paper aims to present a reconfigurable rounding based multiplier with different accuracy levels based on a divide and conquer approach for applications in image processing that is made accuracy-configurable.
Abstract: This paper aims to present a reconfigurable rounding based multiplier with different accuracy levels. It is based on a divide and conquer approach for applications in image processing. Our proposed approach divides the multiplicand and multiplier into two halves. Each half is multiplied with the other and our architecture is made accuracy-configurable. Further, due to rounding based approach, our approximate multiplication technique generates results faster. Based on our experiments, we observe that our proposed multiplier is 26.3% more accurate on an average compared to other state-of-the-art approximate multipliers for 8-bit operations.

2 citations

Posted Content
TL;DR: The proposed paradigm mitigates major weaknesses of hard realization by alleviating incompatibilities with today's soft and bio-inspired algorithms such as artificial neural networks, fuzzy systems, and human sense signal processing applications, and resolving the destructive inconsistency with unreliable nanotechnologies.
Abstract: Researchers traditionally solve the computational problems through rigorous and deterministic algorithms called as Hard Computing. These precise algorithms have widely been realized using digital technology as an inherently reliable and accurate implementation platform, either in hardware or software forms. This rigid form of implementation which we refer as Hard Realization relies on strict algorithmic accuracy constraints dictated to digital design engineers. Hard realization admits paying as much as necessary implementation costs to preserve computation precision and determinism throughout all the design and implementation steps. Despite its prior accomplishments, this conventional paradigm has encountered serious challenges with today's emerging applications and implementation technologies. Unlike traditional hard computing, the emerging soft and bio-inspired algorithms do not rely on fully precise and deterministic computation. Moreover, the incoming nanotechnologies face increasing reliability issues that prevent them from being efficiently exploited in hard realization of applications. This article examines Soft Realization, a novel bio-inspired approach to design and implementation of an important category of applications noticing the internal brain structure. The proposed paradigm mitigates major weaknesses of hard realization by (1) alleviating incompatibilities with today's soft and bio-inspired algorithms such as artificial neural networks, fuzzy systems, and human sense signal processing applications, and (2) resolving the destructive inconsistency with unreliable nanotechnologies. Our experimental results on a set of well-known soft applications implemented using the proposed soft realization paradigm in both reliable and unreliable technologies indicate that significant energy, delay, and area savings can be obtained compared to the conventional implementation.

1 citations

Proceedings ArticleDOI
03 Mar 2021
TL;DR: In this paper, an approximate multiplier (SEAMBA) is proposed, which is called semi-approximate because it has both accurate and approximate components in its design, and a block-based mechanism alongside rounding is used here so as to target specific block approximations.
Abstract: Approximate computing in recent times has evolved in a humongous manner due to the extensive error-resilient capability of various data-intensive applications. In this paper, an approximate multiplier (SEAMBA) is proposed. It is called semi-approximate because it has both accurate and approximate components in its design. A block-based mechanism alongside rounding is used here so as to target specific block approximations. Experimental results show that SEAMBA is more accurate compared to other state-of-the-art approximate multipliers and it has a delay that is lesser than them by 24.7% on an average.
Proceedings ArticleDOI
01 Jul 2022
TL;DR: This paper proposes an hardware implementation of HCD that relies on approximating the intermediate multiplication operations using Dynamic Range Unbiased Multiplier (DRUM), and explores how the errors due to approximate operations propagate to the corner response and attempts to find a threshold that adapts to this inaccuracy across images.
Abstract: Image processing algorithms with intrinsic robustness to errors can be approximated for significant resource and energy savings while still meeting the end-user requirements. FPGA-based implementations can increase their suitability for real-time high-speed multimedia applications by leveraging Approximate Computing, an independent field that explores methods to reduce computation costs by allowing minor degradation in intermediate computations. With high volume of pixel level computations, corner detection algorithms such as the Harris Corner Detector (HCD), offer wide range of targets for such strategies. In this paper, we propose an hardware implementation of HCD that relies on approximating the intermediate multiplication operations using Dynamic Range Unbiased Multiplier (DRUM). With run-time configurable bit-width control of DRUM instances, the visual quality of outputs is shown to depend on the varying accuracy of the corner response. We explore how the errors due to approximate operations propagate to the corner response and attempt to find a threshold that adapts to this inaccuracy across images. The experimental results for implementations on Virtex-7 and Zynq-7000 FPGA devices show that our approximate architecture can match the performance of other HCD implementations while hardly utilizing any on-board memory and signal processing resources. Synthesis results show that the proposed implementation achieves over 60% increase in maximum frequency compared to the base implementation. Finally, the quality metric analysis facilitates the selection of approximate configuration suited to the needs of an application.