Shizheng Yang

Bio: Shizheng Yang is an academic researcher from Xidian University. The author has contributed to research in topics: Molecular beam epitaxy & Integrated circuit. The author has an hindex of 3, co-authored 11 publications receiving 30 citations.

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Abstract: Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Abstract: A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works.

Method for predicting temperature distribution of semiconductor device

Abstract: The invention discloses a method for predicting temperature distribution of a semiconductor device, and relates to the technical field of integrated circuit analysis. The method comprises the main steps of (1) acquiring model parameters of the active device from a chip, (2) establishing a model of the device in COMSOL, and conducting finite element temperature analysis on the model, (3) conducting function fitting on the temperature distribution of the device in MATLAB, and (4) substituting the power consumption, the area of a heating zone, the ambient temperature and other arguments of the actual active device into a temperature function expression formula, and obtaining the temperature distribution of the device. The method for predicting temperature distribution of a semiconductor device can be widely applied to the field of integrated circuit analysis, and compared with the traditional finite element analysis method, the method for predicting temperature distribution of a semiconductor device has the advantages of omitting the processes of entity model establishment and mesh generation and saving plenty of computer hardware resources and calculation time, and the method for predicting temperature distribution of a semiconductor device can achieve the temperature analysis of the semiconductor device simply, quickly and efficiently.

Effect of Thickness of InP Nucleation Layer on the Two-Step Growth of InP on Si(001)

Abstract: InP nucleation layers with different thicknesses were grown on Si(001) substrates by gas-source molecular beam epitaxy (GSMBE), and the two-step growth technique was used to overcome the large lattice mismatch (8%) between the InP nucleation layer and Si substrate. The surface morphology and microstructure were investigated by using an atomic force microscope (AFM) and transmission electron microscopy (TEM). High-resolution X-ray diffraction (HR-XRD) measurements were carried out to characterize the crystal quality. It was found that a too thin nucleation layer will lead to an uneven distribution of atoms on the surface, resulting in a poor crystalline quality of the InP epitaxial layer. The thicker the low-temperature nucleation layer is, the better the crystallization quality of the InP high-temperature layer will be.

High-sampling-rate broadband track and hold circuit

Abstract: The invention discloses a high-sampling-rate broadband track and hold circuit and relates to the technical field of electrons. The track and hold circuit comprises an input buffer unit IB, a track/hold switch T/H, a holding capacitor CH and an output buffer unit OB. A full-differential circuit structure is introduced to realize good common-mode noise suppression ability; through the input and output buffers having emitter degeneration resistors, linearity of the track and hold circuit is improved; an improved switch emitter follower having a Schottky diode is adopted as a track and hold switch, so that circuit stability is improved; and the track and hold circuit is designed by utilizing a GaAs HBT device having high cut-off frequency and good base-emitter match, thereby solving the defects of low sampling rate and narrow bandwidth of an existing sampling and hold circuit.

Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

Abstract: Based on an analytical surface potential model incorporating the channel inversion carriers, a physics-based terminal capacitance model with closed-form solutions for a hetero-gate-dielectric (HGD) tunnel field-effect transistor (TFET) is developed for the first time. Good agreements between the proposed model and the numerical simulations have been achieved in all operation regimes and for different HGD structures. The developed model without involving any iterative process can be easily applied to the widely used SPICE simulations and would be helpful for the transient performance of TFET-based circuits.

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Abstract: A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works.

Characteristics of InAs/GaSb Line-Tunneling FETs With Buried Drain Technique

Abstract: The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The “cantilever” or “airbridge” structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the $\text{P}\boldsymbol +$ source and effectively cuts the leakage current path off. The InAs $\boldsymbol /$ GaSb LTFETs with this buried drain technique exhibits ${I}_{ \mathrm{\scriptscriptstyle ON}} \boldsymbol / {I}_{ \mathrm{\scriptscriptstyle OFF}} > {10}^{{7}}$ and SS $\boldsymbol /$ dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications.