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Shouqian Yu

Bio: Shouqian Yu is an academic researcher from Peking University. The author has contributed to research in topics: Control theory & Synchronization. The author has an hindex of 1, co-authored 2 publications receiving 26 citations.

Papers
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Proceedings ArticleDOI
23 May 2007
TL;DR: A multi-channel UART controller based on FIFO (first in first out) technique and FPGA (field programmable gate array) to implement communication in modern complex control systems quickly and effectively is presented.
Abstract: To meet modern complex control systems communication demands, the paper presents a multi-channel UART controller based on FIFO (first in first out) technique and FPGA (field programmable gate array). The paper presents design method of asynchronous FIFO and structure of the controller. This controller is designed with FIFO circuit block and UART (universal asynchronous receiver transmitter) circuit block within FPGA to implement communication in modern complex control systems quickly and effectively. Form the communication sequence diagrams, it is easily to know that this controller can be used to implement communication when master equipment and slaver equipment are set at different Baud Rate. It also can be used to reduce synchronization error between sub-systems in a system with several sub-systems. The controller is reconfigurable and scalable.

31 citations

Proceedings ArticleDOI
23 May 2007
TL;DR: Simulation results show that the fuzzy neural network controller with a simple and intuitive structure can keep an invert-pendulum system completely in stabilization.
Abstract: This paper reviews the current fuzzy control technology from the engineering point of view, and presents a new method for using parallel fuzzy neural network for invert-pendulum. The neural network is designed to be a treble forward direction network structure with two inputs and three outputs. Considering the reiteration of neural network training, a fuzzy controller is added which is used to compensate the output of the neural network controller. It stabilizes the output variable at some minimum value. Then the weights of neural network are kept at a stable value and the whole controller retains in stabilization. Simulation results show that the fuzzy neural network controller with a simple and intuitive structure can keep an invert-pendulum system completely in stabilization.

Cited by
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Proceedings ArticleDOI
02 Dec 2013
TL;DR: This work investigates whether this simple clocked hardware protocol can be advantageously implemented using asynchronous design techniques, and implements and compared a full duplex clocked and asynchronous UART.
Abstract: Universal Asynchronous Receiver Transmitter (UART) implements serial communication between peripherals and remote embedded systems. The UART protocol is defined based on fixed frequencies with a sampling method to achieve robustness under reasonable frequency variations between systems. Such design specifications are natural for clocked domains. This work investigates whether this simple clocked hardware protocol can be advantageously implemented using asynchronous design techniques. A full duplex clocked and asynchronous UART are implemented and compared. The asynchronous design results in average power of about one-fourth that of the clocked design under standard operating modes.

20 citations

Proceedings ArticleDOI
16 Jul 2012
TL;DR: To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol.
Abstract: To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol. Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.

12 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: To meet the standard modern system wireless communication demands, the paper represents the implementation of bidirectional shift converter technique with FIFO circuit block and UART circuit block through FPGA device using Verilog HDL language to be applied in embedded system converter RS232 to USB (Universal Serial Bus).
Abstract: To meet the standard modern system wireless communication demands, the paper represents the implementation of bidirectional shift converter technique with FIFO circuit block and UART (Universal Asynchronous Receiver Transmitter) circuit block through FPGA device using Verilog HDL language to be applied in embedded system converter RS232 to USB (Universal Serial Bus) Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality

5 citations

Proceedings ArticleDOI
26 Aug 2009
TL;DR: To meet the complex requirements of the miniature embedded integrated (INS/GPS) navigation system based on DSP, all peripheral circuits were integrated in single chip of FPGA, such as logic control module, serial/parallel data conversion and FIFO, etc.
Abstract: To meet the complex requirements of the miniature embedded integrated (INS/GPS) navigation system based on DSP, all peripheral circuits were integrated in single chip of FPGA, such as logic control module, serial/parallel data conversion and FIFO(First In First Out), etc. The multi-channel UART(Universal Asynchronous Receiver Transmitter) consists of the data conversion circuit and FIFO. In addition, the ping-pong buffer storages were assigned in the internal RAM of DSP so that EDMA controller of DSP could transmit data between the FIFOs of UART and the ping-pong buffer storages without CPU intervention. All methods above could relieve the redundant overhead of CPU on data transmission. The test results indicate that the scheme makes multi-channel UART operate at 460.8 kbps steadily by control of EDMA when CPU processes data at the same time. In this way, the real-time performance and reliability of the system can be enhanced effectively and CPU can be devoted to navigation algorithms and Kalman filtering.

4 citations

Proceedings ArticleDOI
15 Nov 2010
TL;DR: The two protocols: Controller Area Network (CAN) and Universal Asynchronous Receiver and Transmitter (UART) are studied and how to design a non data loss communication system working at the highest transmission rate is described.
Abstract: This paper first studies the two protocols: Controller Area Network (CAN) and Universal Asynchronous Receiver and Transmitter (UART). In particular, it focuses on their effective data transmission rates and ratios. Next it lists the common Microcontrollers (MCU) to estimate their highest baud rates. Furthermore, this paper describes how to design a non data loss communication system working at the highest transmission rate. Finally, this paper demonstrates a complete measurement system using an Altera FPGA, an Atmel CAN MCU and an NI USB CAN interface and verifies the measurement results before coming to a conclusion.

3 citations