An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A systematic study of GaN-based heterostructure field-effect transistors with an insulating carbon-doped GaN back barrier for high-voltage operation is presented. The impact of variations of carbon doping concentration, GaN channel thickness, and substrates is evaluated. Tradeoff considerations in on-state resistance versus current collapse are addressed. Suppression of the off-state subthreshold drain-leakage currents enables a breakdown voltage enhancement of over 1000 V with a low on-state resistance. Devices with a 5-μm gate-drain separation on semi-insulating SiC and a 7-μm gate-drain separation on n-SiC exhibit 938 V and 0.39 mΩ·cm2 and 942 V and 0.39 m Ω·cmcm2, respectively. A power device figure of merit of ~ 2.3 × 109 V2/Ω·cm2 was calculated for these devices.

AlGaN/GaN/GaN:C Back-Barrier HFETs With Breakdown Voltage of Over 1 kV and Low $R_{\scriptscriptstyle{\rm ON}} \times A$

In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer

Nitride semiconductor device

Disclosed is a nitride semiconductor device, which has a semiconductor multilayer body (103) that includes a first nitride semiconductor layer (104) and a second nitride semiconductor layer (105) which are sequentially formed on a substrate (101). On the semiconductor multilayer body (103), a p-type third nitride semiconductor layer (108) is selectively formed, and on the third nitride semiconductor layer (108), a gate electrode (109) is formed. On the both sides of the third nitride semiconductor layer (108) on the semiconductor multilayer body (103), a first ohmic electrode (106) and a second ohmic electrode (107) are formed, respectively. The first gate electrode (109) is in Schottky-contact with the third nitride semiconductor (108).

Nitride semiconductor device and method for manufacturing same

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, VBD saturates at ~700 V at a gate-drain distance (LGD) ≥ 8 μm. However, after etching away the substrate locally, we measure a record VBD of 2200 V for the devices with LGD = 20 μm. Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties.

Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2- $\mu\hbox{m}$ Buffer Thickness by Local Substrate Removal

In this paper, GaN-based MIS-HFET devices on 4-inch Si substrates were fabricated, and the device characteristics were examined. As a result, the breakdown voltage was improved to be over 2.45 kV using high-resistive carbon doped buffer layers with a larger thickness of over 7.3 µm. The maximum drain current was estimated to be over 115 A using MIS-structures. A trade-off between the specific on-resistance (RonA) and the breakdown voltage (Vb) was improved using carbon doped buffer layers, resulting in obtaining RonA = 5.9 mΩcm2 and Vb = 1730 V simultaneously with the gate-width of a 340 mm. Furthermore, the field-plate structure was introduced into MIS-HFET structures. We have examined the suppression of a current collapse phenomenon owing to the combination of the gate field-plate structure and a conductive Si substrate with MIS-HFET devices.

High-power AlGaN/GaN MIS-HFETs with field-plates on Si substrates

In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.

GaN-based semiconductor device and method of manufacturing the same

A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse. A method of manufacturing the GaN-based field effect transistor(s) can comprise performing an epitaxial growth of an AlN layer ( 102 ), of a buffer layer ( 103 ), of a channel layer ( 104 ), of a drift layer ( 105 ) and of an electron supplying layer ( 106 ) in such the order on to a substrate ( 101 ) respectively; forming a recess part ( 108 ) thereon; performing an alloying process for performing an annealing in order to obtain an ohmic contact; forming a passivation layer ( 113 ) at a period of performing the annealing in the alloying process in order to protect the electron supplying layer ( 106 ) on to a surface of the recess part ( 108 ), on to the electron supplying layer ( 106 ), on to a source electrode ( 109 ) and on to a drain electrode ( 110 ), respectively; removing the passivation layer ( 113 ); forming a gate insulating film on to a surface at the inner side of the recess part ( 108 ), on to the electron supplying layer ( 106 ), on to the source electrode ( 109 ) and on to the drain electrode ( 110 ), respectively; and forming a gate electrode on to the gate insulating film at a part of the recess part ( 108 ).

Method of manufacturing GaN-based transistors

An efficient method is proposed for the numerical simulation of the bundle-level skin effect and its consequences arising in certain types of litz wires. The method is based on a probabilistic approach. The theory presented allows characterization of the repartition of currents between bundles and predicts some unexpected unique features. The method is tested on a coil unit that is used for inductive wireless power transfer. Simulations are verified by experimental data.

Loss Computation Method for Litz Cables With Emphasis on Bundle-Level Skin Effect

In this paper, GaN-based HFET devices on 4-inch Si substrates were fabricated, and the device characteristics were examined. As a result, the maximum drain current was estimated to be over 115 A using MIS-structures. A trade-off between the specific on-resistance (RonA) and the breakdown voltage (Vb) was improved using carbon doped buffer layers, resulting in obtaining RonA=3D 5.9 mΩcm2 and Vb=3D 1730 V simultaneously with the gate-width of a 340 mm. Furthermore, the gate field-plate structure was introduced into MIS-HFET structures. We have examined the suppression of a current collapse phenomenon owing to the combination of the gate field-plate structure and a conductive Si substrate with MIS-HFET devices.

Shusuke Kaya

Papers

High-power AlGaN/GaN MIS-HFETs with field-plates on Si substrates

GaN-based semiconductor device and method of manufacturing the same

Method of manufacturing GaN-based transistors

Loss Computation Method for Litz Cables With Emphasis on Bundle-Level Skin Effect

High-power AlGaN/GaN HFETs on Si substrates