The power consumption and speed of a device is a crucial factor as most of the designs move towards the system-in-package and system-on-chip products. As the size of the device scale down, speed and power consumption doesn’t go hand in hand. Switching power in a CMOS circuit is a prime component of the total power consumption. This switching power is caused by simultaneous charging and discharging of the load capacitances when the signal undergoes transition. The speed of a digital circuit is determined by how fast the circuit can generate outputs from the given inputs. There are various ways to reduce power consumption such as voltage scaling, clock gating, reversible logic, and so on. For increasing the speed of a circuit, delay inside the logic should be reduced. The choice of a smarter design architecture helps in improving the circuit speed. This work focuses on an ALU design using Vedic algorithm and reversible logic. It aims for better speed and power. The proposed Vedic algorithm based ALU design yields 6.7% decrease in dynamic power and 2.2% decrease in a number of cells used.

Power and Delay Efficient ALU Using Vedic Multiplier

Electronics, and in particular the integrated circuits has been made possible the design of powerful and flexible processors. Having this vision in mind, a dedicated architecture is proposed in this paper which is exclusively used for multiplication of two numbers based on the Vedic sutras. The most significant operation in any signal processing and scientific applications is multiplication. The use of squaring circuits in place of general multipliers can reduce the number of inputs and thereby significantly will reduce the area consumed. To accomplish this, we have implemented Nikhilam Sutra, which is one of the sixteen sutras in Vedic Mathematics. This is dedicated for computing the square of the number. This technique is further extended for finding the product of the binary numbers. The performance for the proposed design is compared with the existing multipliers, on the basis of delay and area utilization. The results prove that the architecture prosed using Nikhilam sutra improves the efficiency considerably. The design has been implemented using Verilog HDL for 8 bit numbers and the synthesis is done using Xilinx ISE 14.5 software.

Design and implementation of high efficiency vedic binary multiplier circuit based on squaring circuits

There is an ever increasing demand for low-power and high-speed designs due to the emergence of portable, handheld gadgets which run on batteries. More and more research works in VLSI are concentrated on different methodologies to reduce the power consumption of a system and also increase its throughput. Multiplication is an important operation in almost all computations. Design of multipliers with low power utilization and increased throughput will lead to systems with reduced power usage and high speed. Vedic Multipliers based on the Urdhava Tiryakbhyam sutra delivers results faster than the customary methods. Reversible logic gates when used in a circuit lead to little or no power dissipation. The paper proposes a system which employs Vedic multipliers and reversible gates to perform multiplications with increased throughput and using very little power. The designed system is optimized by combining the low power strategy of reversible logic and the high speed calculation of Urdhava Tiryakbhyam Vedic multiplier.

Speed and Power Efficient Reversible Logic Based Vedic Multiplier

Vedic Mathematics a method of conceptual calculation also reasoning. It has 16 sutras (formulas) and 13 sub-sutras(corollary). Vedic Mathematics formulas, which are mathematical concepts founded proceeding antediluvian Indian scripts called Veda meaning, knowledge reiterated by SWAMI SRI BHARATI KRISNA TIRTHAJI MAHARAJA. Due to its versatile nature and speed, it applies to many fields. This paper is an array of growth and development in the field of Vedic mathematics with a special focus on the structure of Vedic multipliers and Vedic algorithms like Urdhva Tiriyagbhyam and Nikhilam algorithms. Further an over view of Vedic Mathematics with NEP2020 is deliberated.

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Study of mathematics through indian veda’s : A review

High speed and less area have always been a major concern in VLSI design. With this as a constraint, in this paper a dedicated architecture which is exclusively used for squaring operation has been proposed. Squaring plays a vital role in many signal processing applications and probabilistic analysis in communication systems, where, quite often general multipliers are used although squaring has to be done. This unnecessarily increases the area of the design and also increases the computation time. The principles of Nikhilam Sutra have been leveraged and is extended for squaring binary bits. A comparative study of the projected architecture and the prevailing multipliers, on the premise of delay and space utilization is presented. The simulation outcome proves that the design projected employing Nikhilam sutra improves the performance significantly. The 8-bit architecture has been developed by Verilog HDL and the synthesis is completed using Xilinx ISE - 14.5 software.

Design of an efficient vedic binary squaring circuit

The proposed project utilizes the computational speed advantages of Vedic algorithm and energy optimization benefits of Reversible circuit. The Vedic algorithm optimizes the conventional mathematic computation logic used in the current processors thereby, effectively increasing the speed of computation. The Urdhva Triyambakam method derived from the ancient Indian mathematics will be used in the proposed project. Reversible circuits, on the other hand, reduces the power dissipation incurred due information/bits loss as in the case of an irreversible circuit making way for better power utilization along with reduced heat dissipation. The proposed project introduces the concept of application specific reversibility wherein the logical states belonging only to a particular function of the module is being considered, which significantly impacts in reducing the area limitations of a reversible unit while keeping its power efficiency benefits. The circuit design presented utilizes the above technique mentioned while designing the adder, multiplier along with other modules of an ALU.

Shyam Iyer

Papers

Novel Vedic mathematics based ALU using application specific reversibility