S
Siddarth A. Krishnan
Researcher at IBM
Publications - 103
Citations - 2043
Siddarth A. Krishnan is an academic researcher from IBM. The author has contributed to research in topics: Gate dielectric & Metal gate. The author has an hindex of 24, co-authored 100 publications receiving 1972 citations. Previous affiliations of Siddarth A. Krishnan include SEMATECH.
Papers
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Proceedings ArticleDOI
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
H.S. Yang,R. Malik,Shreesh Narasimha,Yujun Li,Rama Divakaruni,Paul D. Agnello,S. Allen,A. Antreasyan,J.C. Arnold,K. Bandy,Michael P. Belyansky,A. Bonnoit,G.B. Bronner,Victor Chan,X. Chen,Zhihong Chen,Dureseti Chidambarrao,Anthony I. Chou,William F. Clark,S.W. Crowder,Bernard A. Engel,H. Harifuchi,S.F. Huang,R. Jagannathan,F.F. Jamin,Y. Kohyama,H. Kuroda,C.W. Lai,H.K. Lee,W.-H. Lee,E.H. Lim,W. Lai,Anupama Mallikarjunan,K. Matsumoto,A. McKnight,J. Nayak,H.Y. Ng,Siddhartha Panda,Rajesh Rengarajan,M. Steigerwalt,S. Subbanna,Kartik Subramanian,J. Sudijono,G. Sudo,S.-P. Sun,B. Tessier,Yoshiaki Toyoshima,P. Tran,Richard Wise,R. Wong,I.Y. Yang,C. Wann,L.T. Su,Manfred Horstmann,Th. Feudel,A. Wei,Kai Frohberg,G. Burbach,Martin Gerhardt,Markus Lenski,Rolf Stephan,K. Wieczorek,Matthias Schaller,Heike Salz,Jörg Hohage,Hartmut Ruelke,J. Klais,P. Huebler,Scott Luning,R. van Bentum,G. Grasshoff,C. Schwan,E. Ehrichs,S. Goad,J. Buller,Siddarth A. Krishnan,D. Greenlaw,Michael Raab,N. Kepler +78 more
TL;DR: In this article, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow, which results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current improvement of 11%/20%.
Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Journal ArticleDOI
Nucleation and growth study of atomic layer deposited HfO 2 gate dielectrics resulting in improved scaling and electron mobility
Paul Kirsch,Manuel Quevedo-Lopez,H.-J. Li,Y. Senzaki,Jeff J. Peterson,Seung-Chul Song,Siddarth A. Krishnan,Naim Moumen,Joel Barnett,Gennadi Bersuker,P. Y. Hung,Byoung Hun Lee,T. Lafford,Qu-Quan Wang,John G. Ekerdt +14 more
TL;DR: In this article, two atomic layer deposition (ALD) chemistries: tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and HfCl4+H2O+O3 were studied as a function of ALD cycle number on Si(100) surfaces.
Proceedings ArticleDOI
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
Siddarth A. Krishnan,Unoh Kwon,Naim Moumen,Matthew W. Stoker,Eric C. Harley,Stephen W. Bedell,Deleep R. Nair,B. Greene,William K. Henson,Murshed M. Chowdhury,D.P. Prakash,Ernest Y. Wu,Dimitris P. Ioannou,Eduard A. Cartier,Myung-Hee Na,S. Inumiya,Kevin McStay,Lisa F. Edge,Ryosuke Iijima,Jin Cai,Martin M. Frank,M. Hargrove,Dechao Guo,Andreas Kerber,Hemanth Jagannathan,Takashi Ando,Joseph F. Shepard,Shahab Siddiqui,Min Dai,Huiming Bu,J. Schaeffer,Jaeger Daniel,Kathy Barla,Thomas A. Wallner,S. Uchimura,Y. Lee,Gauri Karve,Sufi Zafar,Dominic J. Schepis,Yun-Yu Wang,Ricardo A. Donaton,S. Saroop,P. Montanini,Yue Liang,James H. Stathis,Richard Carter,Rohit Pal,Vamsi Paruchuri,H. Yamasaki,J-H Lee,Martin Ostermayr,J.-P. Han,Yue Hu,Michael A. Gribelyuk,Dae-Gyu Park,X. Chen,Srikanth Samavedam,Shreesh Narasimha,Paul D. Agnello,Mukesh Khare,R. Divakaruni,Vijay Narayanan,Michael P. Chudzik +62 more
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Proceedings ArticleDOI
Fundamental aspects of HfO 2 -based high-k metal gate stack reliability and implications on t inv -scaling
Eduard A. Cartier,Andreas Kerber,Takashi Ando,Martin M. Frank,Kisik Choi,Siddarth A. Krishnan,Barry Linder,Kai Zhao,Frederic Monsieur,James H. Stathis,Vijay Narayanan +10 more
TL;DR: In this paper, a case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric.