Neural networks

A compact 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FET (DG TFETs) with a SiO2/High- ${k}$ stacked gate-oxide structure is proposed in this paper. Poisson’s equation has been solved using parabolic approximation method to model the channel potential. The band-to-band tunneling generation rate has been expressed as a function of channel electric field derived from the channel potential and then integrated analytically over the channel thickness to derive the drain current of the stacked-gate DG TFETs using the shortest tunneling path $(L_{t}^{\min } )$ concept. The effect of source/drain depletion regions has been included for the better accuracy of the proposed model. The maximum transconductance method has finally been used to extract the threshold voltage from the drain current of the device. The effects of various device parameters on the channel potential, drain current, and threshold voltage have been investigated. The model results have been compared with the simulation data obtained using the commercially available ATLAS 2-D device simulator from SILVACO for the validity of the proposed model.

A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO 2 /High- $k$ Stacked Gate-Oxide Structure

The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130 nm, 90 nm, and 65 nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle. It is shown that the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET. Experimental and simulation results are presented for mixed MOSFET/TFET circuits. The usage of the TFET does not cause delay degradation. The static power consumption and signal integrity are improved compared to the CMOS realization.

Scaling properties of the tunneling field effect transistor (TFET) : Device and circuit

The impact of triple metal with unalike work functions on the gate all around (GAA) tunnel FET is studied for the first time in this paper. An analytical model is introduced for surface potential and drain current of GAA triple metal tunnel FET with circular cross section, by using Poisson’s equation and Kane’s model. The modeling results are in good agreement with Synopsys 3-D TCAD results, thereby corroborating our analysis. The different metal work functions assist to create the potential barrier in the channel region to suppress the reverse tunneling from the drain side and also provides a more band bending at source end which revamp the drive current.

Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET

This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and ${10}^{ {4}}~{ \mathrm{\scriptstyle ON}}/{ \mathrm{\scriptstyle OFF}}$ current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ${I}_{D}$ regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.

Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

A 2D analytical tunnel field-effect transistor (FET) potential model with cylindrical gate (CG-TFET) based on the solution of Laplace's equation is proposed. The band-to-band tunneling (BTBT) current is derived by the help of lateral electric field and the shortest tunneling distance. However, the analysis is extended to obtain the subthreshold swing (SS) and transfer characteristics of the device. The dependency of drain current, SS and transconductance on gate voltage and shortest tunneling distance is discussed. Also, the effect of scaling the gate oxide thickness and the cylindrical body diameter on the electrical parameters of the device is analyzed.

https://iopscience.iop.org/article/10.1088/2043-6262/6/3/035005/pdf

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET)

In this work the sensitivity of process parameters like channel length (L), channel thickness (tSi), and gate work function (M) on various performance metrics of an undoped cylindrical gate all around (GAA) metal-oxide-semiconductor field effect transistor (MOSFET) are systematically analyzed. Undoped GAA MOSFET is a radical invention as it introduces a new direction for transistor scaling. In conventional MOSFET, generally the channel doping concentration is very high to provide high on-state current, but in contrary it causes random dopant fluctuation and threshold voltage variation. So, the undoped nature of GAA MOSFET solves the above complications. Hence, we have analyzed the electrical characteristics as well as the analog/RF performances of undoped GAA MOSFET through Sentaurus device simulator.

https://iopscience.iop.org/article/10.1088/2043-6262/6/3/035010/pdf

Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime

A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping

In the proposed work an analytical model of a p-channel dual material gate all around tunnel FET (DMGAA-TFET) is presented and its performance is compared with the conventional GAA-TFET. The electrostatic potential profile of the model is obtained using 2-D Laplace's solution in the cylindrical coordinate system. A quantitative study of the drain current has been carried out using electric field in the z-axis and tunneling path. However the potential and current analysis is prolonged to different combinations of gate length in the DMGAA-TFET model. The results show an improvement in drain current and subthreshold swing as compared to GAA-TFET, which makes this model a potential replacement for low power application. Also the effect of scaling of the gate oxide thickness and cylindrical pillar diameter on the surface potential, initial tunneling point and tunneling current are analyzed.

https://iopscience.iop.org/article/10.1088/2043-6262/7/2/025012/pdf

Sidhartha Dash

Papers

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET)

Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime

A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping

An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET)