S
Simon Deleonibus
Researcher at Commissariat à l'énergie atomique et aux énergies alternatives
Publications - 52
Citations - 805
Simon Deleonibus is an academic researcher from Commissariat à l'énergie atomique et aux énergies alternatives. The author has contributed to research in topics: Metal gate & MOSFET. The author has an hindex of 15, co-authored 52 publications receiving 773 citations.
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Proceedings ArticleDOI
Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance
F. Mayer,C. Le Royer,J.-F. Damlencourt,K. Romanjek,Francois Andrieu,Claude Tabone,Bernard Previtali,Simon Deleonibus +7 more
TL;DR: In this article, the Drift Tunnel FET (DTFET) was proposed to solve the TFET bipolar parasitic conduction by a novel TFET architecture, with improved OFF state control, and demonstrated functional TFET and CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow.
Journal ArticleDOI
Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks
Perrine Batude,X. Garros,Laurent Clavelier,C. Le Royer,J.M. Hartmann,Virginie Loup,Pascal Besson,L. Vandroux,Y. Campidelli,Simon Deleonibus,Fabien Boulanger +10 more
TL;DR: In this article, an electrical model is proposed to give insights on the fundamental mechanisms impacting germanium metal oxide semiconductor (MOS) structures from a careful analysis of these CV measurements.
Proceedings ArticleDOI
FDSOI devices with thin BOX and ground plane integration for 32nm node and below
Claire Fenouillet-Beranger,Stephane Denorme,P. Perreau,C. Buj,O. Faynot,Francois Andrieu,L. Tosti,Sébastien Barnola,T. Salvetat,X. Garros,M. Casse,F. Allain,Nicolas Loubet,Loan Pham-Nguyen,E. Deloffre,Mickael Gros-Jean,Remi Beneyton,C. Laviron,M. Marin,C. Leyris,Sebastien Haendler,Francois Leverd,Pascal Gouraud,P. Scheiblin,L. Clement,Roland Pantel,Simon Deleonibus,Tomasz Skotnicki +27 more
TL;DR: In this paper, the authors compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP) conditions and compare with bulk shrunk technology in terms of variability and noise.
Journal ArticleDOI
The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?
Benjamin Vincent,J.-F. Damlencourt,Yves Morand,A. Pouydebasque,C. Le Royer,Laurent Clavelier,N. Dechoux,P. Rivallin,Tuan Nguyen,Sorin Cristoloveanu,Yves Campidelli,D. Rouchon,M. Mermoux,Simon Deleonibus,D. Bensahel,T. Billon +15 more
TL;DR: In this article, a general study on the germanium condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies is presented.
Journal ArticleDOI
105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers
C. Le Royer,Laurent Clavelier,Claude Tabone,K. Romanjek,Chrystel Deguet,Loic Sanchez,J.M. Hartmann,M.-C. Roure,H. Grampeix,S. Soliveres,G. Le Carval,R. Truche,A. Pouydebasque,M. Vinet,Simon Deleonibus +14 more
TL;DR: In this paper, the authors report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105nm) GeOI pMOSFETs.