Simon Deleonibus

Bio: Simon Deleonibus is an academic researcher from European Automobile Manufacturers Association. The author has contributed to research in topics: MOSFET & Silicon on insulator. The author has an hindex of 25, co-authored 129 publications receiving 1742 citations. Previous affiliations of Simon Deleonibus include French Alternative Energies and Atomic Energy Commission.

A simple and controlled single electron transistor based on doping modulation in silicon nanowires

Abstract: A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and therefore controlled by lithography. The source and drain capacitances have also been characterized. This design could be used to build more complex SET devices.

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

Abstract: Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed

Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?

Abstract: Both CMOS scaling and NEMS sensor devices scaling converge to the same type of sub 100 nm objects. This opens new fields of application for IC chips integrating both complex signal treatment and very highly sensitive sensing functionalities.

Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO 2 gate stack

Abstract: Scalability of both unstrained and strained FDSOI CMOSFETs is explored for the first time down to 2.5 nm film thickness and 18 nm gate length with HfO2/TiN gate stack. Off-state currents in the pA/mum range are achieved for 18 nm short and 3.8nm thin MOSFETs thanks to outstanding electrostatic control: 67 mV/dec subthreshold swing and 75 mV/V DIBL. For such thin bodies, the buried oxide fringing field limitation on DIBL is experimentally evidenced and quantified for the first time. Furthermore, we demonstrate strain induced ION gain as high as 40% on the shortest transistors. An in-depth analysis of this gain as a function of the film thickness is carried out through mobility and ballisticity extractions.

Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit

Abstract: Impact ionization MOSFET (IMOS) is a device that enables to reach subthreshold slopes as small as 5 mV/dec. This device has an asymmetric doping profile, and only a fraction of the channel is covered by the gate. In the first part of this paper, the purpose is to investigate the impact of some geometrical parameters on the IMOS performance: the gate length, the intrinsic length, and the Si film thickness. This study simulates a p-IMOS device on silicon-on-insulator using ATLAS. It is pointed out that the increase of the ratio LG/LIN allows a drop of the bias voltage, but involves a degradation of the subthreshold slope. A thin Si film improves the overall device performance. In the second part, the performance of an IMOS-based inverter is investigated, and for the first time an IMOS ring oscillator is simulated

Silicon quantum electronics

Abstract: This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.

Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

Abstract: This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Academic and industry research progress in germanium nanodevices

Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

A review of emerging non-volatile memory (NVM) technologies and applications

Abstract: This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power ( e.g. , mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g. , neuromorphic computing, hardware security, etc . In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.