S
Sina Shahhosseini
Researcher at University of California, Irvine
Publications - 18
Citations - 112
Sina Shahhosseini is an academic researcher from University of California, Irvine. The author has contributed to research in topics: Computer science & Speedup. The author has an hindex of 5, co-authored 12 publications receiving 53 citations. Previous affiliations of Sina Shahhosseini include Sharif University of Technology.
Papers
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Proceedings ArticleDOI
An Edge-Assisted and Smart System for Real-Time Pain Monitoring
Emad Kasaeyan Naeini,Sina Shahhosseini,Ajan Subramanian,Tingjue Yin,Amir M. Rahmani,Nikil Dutt +5 more
TL;DR: A smart and self-aware system capable of adaptively making a decision at run-time in response to the changes in pain level and context can minimize energy consumption by dynamically offloading tasks to the gateway devices at the edge layer.
Proceedings ArticleDOI
Dynamic Computation Migration at the Edge: Is There an Optimal Choice?
Sina Shahhosseini,Iman Azimi,Arman Anzanpour,Axel Jantsch,Pasi Liljeberg,Nikil Dutt,Amir M. Rahmani +6 more
TL;DR: This paper proposes a static approach to find the optimal computation migration strategy using models known at design-time and proposes a dynamic approach which can adaptively identify the latency optimal computation layer at runtime.
Journal ArticleDOI
Exploring computation offloading in IoT systems
Sina Shahhosseini,Arman Anzanpour,Iman Azimi,Sina Labbaf,Dongjoo Seo,Dongjoo Seo,Sung-Soo Lim,Pasi Liljeberg,Nikil Dutt,Amir M. Rahmani +9 more
TL;DR: The impact of the computation offloading on total application response time in three-layer IoT systems considering more realistic parameters, e.g., application characteristics, system complexity, communication cost, and dataflow configuration is explored.
Posted Content
Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors.
TL;DR: These explorations help designers select the right PQC implementations for making future signal processing applications quantum-resistant, as well as design two high-throughput systolic array polynomial multipliers, including NTT-based and convolution-based, and compare them to the low-cost sequential (non-systolic) N TT-based multiplier.
Proceedings ArticleDOI
Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors
TL;DR: In this article, the authors explore the energy efficiency of polynomial multiplier using systolic architecture for the first time, and design two high-throughput Systolic array Polynomial multipliers, including NTT-based and convolution-based, and compare them to their low-cost sequential (non-systolic) NTTbased multiplier.