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Smruti R. Sarangi

Researcher at Indian Institute of Technology Delhi

Publications -  132
Citations -  2927

Smruti R. Sarangi is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Computer science & Cache. The author has an hindex of 18, co-authored 111 publications receiving 2310 citations. Previous affiliations of Smruti R. Sarangi include IBM & University of Illinois at Urbana–Champaign.

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Journal ArticleDOI

Internet of Things: Architectures, Protocols, and Applications

TL;DR: This survey paper proposes a novel taxonomy for IoT technologies, highlights some of the most important technologies, and profiles some applications that have the potential to make a striking difference in human life, especially for the differently abled and the elderly.
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VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

TL;DR: In this paper, a microarchitecture-aware model for process variation is proposed, including both random and systematic effects, and the model is specified using a small number of highly intuitive parameters.
Proceedings ArticleDOI

ReCycle: pipeline adaptation to tolerate process variation

TL;DR: ReCycle, an architectural framework that comprehensively applies cycle time stealing to the pipeline - transferring the time slack of the faster stages to the slow ones by skewing clock arrival times to latching elements after fabrication, completely reclaiming the performance losses due to variation.
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Virtual base station pool: towards a wireless network cloud for radio access networks

TL;DR: The first TDD WiMAX SDR BS implemented on a commodity server, in conjunction with a novel design of a remote radio head (RRH) is introduced, and the first working prototype of a virtual BS (VBS) pool is presented, exploring the systems challenges in supporting a VBS pool on multi-core IT platforms.
Proceedings ArticleDOI

EVAL: Utilizing processors with variation-induced timing errors

TL;DR: An effective technique to maximize performance and minimize power in the presence of variation-induced errors, namely High-Dimensional dynamic adaptation is introduced, which increases processor frequency by 56% on average, allowing the processor to cycle 21% faster than without variation.