Sonal Singhal

Bio: Sonal Singhal is an academic researcher from Shiv Nadar University. The author has contributed to research in topics: Negative-bias temperature instability & Piecewise. The author has an hindex of 2, co-authored 6 publications receiving 8 citations.

Correlation of Dynamic and Static Metrics of SRAM Cell under Time-Zero Variability and After NBTI Degradation

Abstract: Static metrics are often used to characterize read stability and write-ability of an SRAM cell. In this paper, two major dynamic SRAM metrics: critical read stability (TREAD) and critical writeability (TWRITE) are discussed and correlated with static metrics. For correlation between dynamic and static metrics, variability analysis is carried out at time-zero and after NBTI degradation of the SRAM cell. Shift in correlation factor is compared for before and after NBTI degradation. Assessment of correlation between dynamic and static metrics is used to identify those static metrics which best capture the dynamic behavior of the cell.

Analyzing Impact of NBTI and Time-Zero Variability on Dynamic SRAM Metrics

Abstract: Critical Read Stability (T READ ) and Critical Writeability (T WRITE ) are two SRAM metrics which can characterize the dynamic behavior of read and write operations. In this paper, the impact of NBTI on T READ and T WRITE is shown. Worst-case use conditions are identified by varying the relative degradation of the two p-FETs. Monte-Carlo simulations using foundry models (High-k Metal Gate planar MOSFET) are performed to analyze time-zero variability for different use conditions. The dynamic metrics T READ and T WRITE are correlated with static metrics SVNM and BWTV respectively for worst-case use conditions. Degradation trend of T READ and T WRITE is then discussed for worst and symmetric NBTI degradation cases by varying ΔV TH .

Analyzing the impact of nbti and process variability on dynamic sram metrics under temperature variations

Abstract: Continuous scaling of CMOS technology has led to reliability issues and process variability that affect the circuit performance of the SRAM cell. The dynamic behavior of SRAM cells are characterized by critical read-stability (Tread) and critical write-ability (Twrite) while the Static Noise Margins (SNMs) are deduced by the static metrics that are the key performance metrics. The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions. Degradation due to NBTI is incorporated by considering different activity factors (α) for the dynamic metrics. Time-zero or process variability is performed for fresh-case, symmetric and asymmetric degradation by Monte Carlo run simulations using foundry models in addition to examining the effect of correlation with their corresponding static metrics.

Investigating the impact of bti and hci on log-domain based mihalas–niebur neuron circuit

Abstract: Neuromorphic circuits are becoming quite popular due to their ability to mimic the structure and behavior of human brain. Current research focuses on approximating spiking biological neuron behavior. Various neuron models have been proposed in the past that aid in investigating the behavior of neuronal systems mathematically. Mihalas–Niebur (MN) neuron model is one among them. In this paper log-domain based MN neuron model is implemented at 45 nm technology node. The paper studies the effects of process-temperature variations and also investigates the impact of Hot Carrier Injection (HCI), Bias Temperature Instability (BTI) on the performance of MN circuit. Average power consumption and spiking frequency are chosen as key performance measures to analyze the circuit performance before and after degradation.

Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics

Abstract: Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined im...

Analyzing Impact of NBTI and Time-Zero Variability on Dynamic SRAM Metrics

Abstract: Critical Read Stability (T READ ) and Critical Writeability (T WRITE ) are two SRAM metrics which can characterize the dynamic behavior of read and write operations. In this paper, the impact of NBTI on T READ and T WRITE is shown. Worst-case use conditions are identified by varying the relative degradation of the two p-FETs. Monte-Carlo simulations using foundry models (High-k Metal Gate planar MOSFET) are performed to analyze time-zero variability for different use conditions. The dynamic metrics T READ and T WRITE are correlated with static metrics SVNM and BWTV respectively for worst-case use conditions. Degradation trend of T READ and T WRITE is then discussed for worst and symmetric NBTI degradation cases by varying ΔV TH .

Analyzing the impact of nbti and process variability on dynamic sram metrics under temperature variations

Abstract: Continuous scaling of CMOS technology has led to reliability issues and process variability that affect the circuit performance of the SRAM cell. The dynamic behavior of SRAM cells are characterized by critical read-stability (Tread) and critical write-ability (Twrite) while the Static Noise Margins (SNMs) are deduced by the static metrics that are the key performance metrics. The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions. Degradation due to NBTI is incorporated by considering different activity factors (α) for the dynamic metrics. Time-zero or process variability is performed for fresh-case, symmetric and asymmetric degradation by Monte Carlo run simulations using foundry models in addition to examining the effect of correlation with their corresponding static metrics.

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

Abstract: The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.