This paper presents a new ultra-low power double-tail latched comparator suited for biomedical applications. The proposed comparator benefits from a positive feedback to achieve high resolution with low kickback noise. It is shown by time analysis and simulation that the delay time is significantly reduced compared to a conventional double-tail latched comparator. The presented circuit is designed and simulated in 0.18-μm CMOS technology. The post-layout simulation results show that the designed comparator consumes only 1.56 nW power, at 600 mV supply voltage and 100 kHz clock frequency. This amount is 54.35 % of power consumption of a conventional double-tail latched comparator with the same input referred offset of 7.5 mV. Furthermore, the proposed circuit provides a self-neutralization technique which results 8.8 % reduction of kick-back noise in comparison to the conventional latched comparator. The maximum clock frequency of this circuit is 200 MHz at 1 V supply voltage. The proposed circuit has a power-delay product of 0.0172 fJ at 100 kHz clock frequency. The proposed comparator is well designed to operate with supply voltages between 400 mV and 1 V.

Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications

A fully on-chip, low-power and small area CMOS Relaxation Oscillator (ROSC) with voltage integral feedback structure and a new Bandgap Reference voltage (BGR) for accurate oscillation frequency independent of the PVT and comparator's delay variations is presented. The designed circuit uses a new bandgap reference to generate the reference voltage required by relaxation oscillator which allow variations due to voltage and temperature to be compensated. Another merit of this oscillator is that the phase noise at low-offset frequency is suppressed by the voltage integral feedback circuit. The frequency of the relaxation oscillator is determined by the RC response time. Thus, the current and capacitance are controlled by temperature and process compensation circuits to compensate for the frequency variation. The ROSC is implemented in a 0.18µm CMOS technology and its active area is 0.14mm2. The target frequency is 25MHz and current consumption is 22µA, where V DD is 1.8V. The oscillation frequency variation for V DD ranges from 1.4 to 1.9V is 0.2% and for temperature ranges from −40 to 125°C is 0.18%.

A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator

A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications

this paper presents a modified technique of power reduction for the preamplifier based dynamic latch comparator. The comparator presented in this paper is having a preamplifier, which is followed by a dynamic latch topology. The comparator is having cross coupled latch to achieve high speed and at a same time kickback effect is also reduced. A modified power control technique is presented to minimize the power consumption, having good reduction in the power compared to other technique presented in the literature. The rail to rail input range and low power comparator which can be suitably used in low-to-medium speed Analog to Digital Converters is implemented in 90nm technology using HSPICE. The simulation results have shown that the power consumption of comparator is 916.9μw at the clock frequency of 200MHz and 1V supply voltage with a delay of 80.3ps

Implementation of Low Power Rail-To-Rail Dynamic Latch Comparator With Modified Adaptive Power Control Technique

This paper presents characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC. Overall performance of any ADC in terms of speed, resolution and power consumption highly depends on the underlying comparator being used. In this paper, better structure of comparator is implemented and analyzed, which is a combination of modified SR latch and sense amplifier. The comparator is built up by preamplifier and positive feedback latch (back-to-back connected inverter) to enhance the speed. The output of latch is given to the modified SR latch, which provides stable output signal compare to that of conventional dynamic latch structure. The implementation is carried out in 90nm technology in Mentor Graphics' IC Studio tool and simulation is done in Eldo tool.

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.

Song Lan

Papers

An ultra low-power rail-to-rail comparator for ADC designs