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Spyridon Skordas

Bio: Spyridon Skordas is an academic researcher from IBM. The author has contributed to research in topics: Wafer & Wafer bonding. The author has an hindex of 11, co-authored 71 publications receiving 779 citations. Previous affiliations of Spyridon Skordas include GlobalFoundries & State University of New York System.


Papers
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Proceedings ArticleDOI
05 Jun 2017
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Abstract: In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

547 citations

Proceedings ArticleDOI
01 Dec 2016
TL;DR: In this paper, the authors present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology.
Abstract: We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

97 citations

Patent
27 Jun 2012
TL;DR: In this paper, the authors propose a method for forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate and a first wiring layer over the alignment via.
Abstract: A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.

49 citations

Journal ArticleDOI
TL;DR: In this article, the metastable impact electron spectroscopy (MIES) and ultraviolet photoemission (UPS) (He ∗ 1s2s) spectra for clean and cesiated TiO 2 (110) and Cs/TiO 2(110) were reported.

43 citations

Patent
30 May 2013
TL;DR: In this paper, a metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and surfaces of a dielectric material layer embedding the copper-base metal pads in each of two substrates to be subsequently bonded.
Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

37 citations


Cited by
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Journal ArticleDOI
Ulrike Diebold1
TL;DR: Titanium dioxide is the most investigated single-crystalline system in the surface science of metal oxides, and the literature on rutile (1.1) and anatase surfaces is reviewed in this paper.

7,056 citations

Journal ArticleDOI
01 Sep 2019-Nature
TL;DR: The opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems are reviewed, and the prospects for computational and non-computational applications are considered.
Abstract: The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

804 citations

Journal ArticleDOI
TL;DR: In this paper, a review of metal-oxide interfaces at temperatures below 1000 ǫC is presented, with special emphasis on model systems like ultrathin metal overlayers or metal nanoclusters supported on well-defined oxide surfaces.

673 citations

Journal ArticleDOI
TL;DR: In this paper, the authors review how metal oxide-based gate dielectrics emerged from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning.
Abstract: The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO 2 in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO 2 emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high- k materials.

450 citations