Showing papers by "Srinivas Devadas published in 1988"

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

Abstract: The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multilevel logic optimization. Results over a wide range of benchmarks which prove the efficacy of the proposed techniques are presented. Literal counts averaging 20%-40% less than other state-assignment programs have been obtained. >

Test generation for sequential circuits

Abstract: An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >

Decomposition and factorization of sequential finite state machines

Abstract: Algorithms are proposed for decomposing a finite-state machine into smaller interacting machines so as to optimize area and performance of the eventual logic implementation Cascade decomposition algorithms, which decompose a given machine into independent and dependent components, have been proposed in the past The authors propose a more powerful form of decomposition where both components of the decomposed machine interact with each other Experimental results indicate that this decomposition technique for state machine decomposition is superior to cascade decomposition techniques It is the premise of this study that optimal state assignment corresponds to finding an optimal multiple general decomposition of a finite-state machine State assignment techniques that target two-level and multilevel implementations based on state machine factorization algorithms followed by state assignment algorithms are presented It is rigorously proved that one-hot encoding a nontrivially factored machine is guaranteed to produce a better result than one-hot encoding the original machine for the two-level case >

On the verification of sequential machines at differing levels of abstraction

Abstract: An algorithm is presented for the verification of the equivalence of two sequential circuit descriptions at the same of differing levels of abstraction, namely, at the register-transfer (RT) level and the logic level. The descriptions represent general finite automata at the differing levels. A finite automaton can be described in ISP-like language and its equivalence to a logic level implementation can be verified using this algorithm. Two logic-level automata can be similarly verified for equivalence. The technique is shown to be computationally efficient for complex circuits. The efficiency of the algorithm lies in the exploitation of don't care information derivable from the RT or logic-level description during the verification process. Using efficient cube enumeration procedures at the logic level, the equivalence of finite automata with a large number of states in small amounts of CPU time was verified. A two-phase enumeration-simulation algorithm for verifying the equivalence of two logic-level finite automata with the same or differing number of latches is also presented. >

An incomplete scan design approach to test generation for sequential machines

Abstract: An incomplete scan design approach to sequential test generation is presented. This approach represents a significant departure from previous methods. First, using an efficient sequential testing algorithm, test sequences are generated for a large number of possible faults in the given sequential circuit. A minimal subset of memory elements is then found, which if made observable and controllable will result in easy detection of the sequentially redundant and irredundant but difficult-to-defect faults. The deterministic test generation algorithm is again used to generate tests for these faults in the modified circuit (the circuit with the identified memory elements made scannable). Detection of all irredundant faults can be guaranteed as in the complete scan design case, but at significantly less area and performance cost. >

Synthesis and optimization procedures for fully and easily testable sequential machines

Abstract: A synthesis procedure is described that produces an optimized fully and easily testable logic implementation of a sequential machine from a state transition graph description of the machine. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic. No access to the memory elements is required. The test sequences for these faults can be obtained using combinational test generation techniques alone. It is shown that an intimate relationship exists between state assignment and the testability of a sequential machine. A technique is also presented of don't-care minimization and added observability which ensures fully testable machines. >

Boolean decomposition of programmable logic arrays

Abstract: The authors present algorithms for Boolean decomposition, which decompose a two-level logic function into a cascade of smaller two-level logic functions, such that the overall area of the resulting logic network is minimized. The algorithms are based on multiple-valued minimization. Given a PLA (programmable logic array), a subset of inputs to the PLA is selected. This selection step incorporates a novel algorithm which selects a set of inputs such that the cardinality of the multiple-valued cover, produced by representing all combinations of these inputs as different values of a single multiple-valued variable, is much smaller than the original binary cover cardinality. A relatively small size for the multiple-valued cover implies that the number of good Boolean factors contained in this subset of inputs are re-encoded to satisfy the constraints given in the multiple-valued cover, thus producing a binary cover for the original PLA whose cardinality equals the multiple-valued cover cardinality. >

Boolean decomposition in multi-level logic optimization

Abstract: Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic network. Given a two-level logic function, a subset of inputs to the function is selected such that the number of good Boolean factors contained in this subset of inputs is large. If the targeted implementation is a set of interconnected PLAs, the different cube combinations given by the subset of inputs are re-encoded to reduce the number of product terms in the logic function. A novel algorithm for the re-encoding is given that is based on the notion of partial satisfaction of constraints. Algorithms have been developed that identify a set of factors which maximally decrease the literal count of the logic network when they are used as strong divisors. Results obtained on several benchmark examples that illustrate the efficacy of the techniques are presented. >

Optimal logic synthesis and testability: two faces of the same coin

Abstract: The relationships between test generation and logic minimization are described. An overview of the state of the art in combinational and sequential logic synthesis is provided. Combinational logic synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination logic can be obtained as a by-product of the logic minimization step. Equally intimate relationships between the problems of sequential logic synthesis and sequential test generation are envisioned. A recently developed synthesis technique of constrained state assignment and logic optimization which ensures fully testable sequential machines is described briefly. >

Techniques for multilayer channel routing

Abstract: The techniques described have been implemented in a multilayer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problems into two-layer and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2 (see ibid., vol.CAD-4, no.3, p.208-19, 1985). In particular, a three-dimensional maze router is used for the vertical connections; this methodology is effective even when cycle constraints are present. Chameleon has produced optimal results on a wide range of industrial and academic examples for a variety of layer and pitch combinations, and can handle a variety of technology constraints. >

Logic Verification, Testing and their Relationship to Logic Synthesis

Abstract: Much work has gone into automating the integrated circuit (IC) design process over the past few years (e.g. [1] [2] [3]). A variety of Computer-Aided Design (CAD) tools for the logic [4] [5] and physical design [6] of integrated circuits have been developed. It is clear that an integrated set of computer design aids coupled with an unified approach to data management is essential for VLSI design. To this end, research has focused on IC synthesis systems [7] i.e. systems which can automatically generate functionally correct mask-level layout of integrated circuit chips from high level, programming language-like specifications.

Critical Problems in Very Large Scale Computer Systems

Abstract: : This is the first semiannual report on this contract. The purpose of the present contract is to investigate limiting technologies for a very large computer system, one which, if built during the mid 1990's, would be so large that the nation could only afford one or two of them. The purpose of this contract is to investigate plausibility, which is defined as the step before feasibility. Once plausibility is demonstrated, then separate efforts at demonstrating feasibility and then design and manufacture would be appropriate. It is estimated that the cost of such 'building-size computer' would be in excess of $1,000,000.000. Six critical areas were identified, and work is in progress in each of these areas. The six areas, and the MIT faculty members who are working in each of the areas, are listed in the chart. The format of this report is based on this table. The work in circuits is a combination of improved techniques in waveform bounding and new ideas in LU factorization and relaxation methods. It has been found that in the context of highly parallel computation, the Gauss-Jacobi technique is never inferior to the Gauss-Seidel technique. Prototype circuits for a proposed processing element have been fabricated, and are under evaluation. The investigation of communications topology and related architectural concerns centers around two projects. In one of them, the Message- Driven Processor is the object of study.

Critical problems in very-large-scale computer systems. Semiannual technical report, 1 April-30 September 1988

Abstract: The research vehicle for this contract is the largest possible computer that could be conceived for the mid to late 1990s. The technical challenges of such a machine serve as the guiding stimulus for the research carried out and reported here. This machine is forecast to occupy a 14-story building, to cost upwards of $1,000,000,000, and to be so colossal that the nation can only afford one or two of them. The available chip technology and machine size are consistent with a million FLOPS and a million billion bytes of memory. It will dissipate 50 megawatts of power using CMOS technology. Communication across the machine will be much slower than computation at a node. The architecture, software, interconnect technology, packaging, and operating system are unknown. This investigation deals with hardware technology, software techniques, programming algorithms, communications, processing elements, and applications. This research will determine the plausibility (not feasibility) of such a machine. Progress in these various areas are highlighted in the individual sections below.