Showing papers by "Srinivas Devadas published in 1999"

Simulation vector generation from HDL descriptions for observability-enhanced statement coverage

Abstract: Validation of RTL circuits remains the primary bottleneck in improving design turnaround time, and simulation remains the primary methodology for validation. Simulation-based validation has suffered from a disconnect between the metrics used to measure the error coverage of a set of simulation vectors, and the vector generation process. This disconnect has resulted in the simulation of virtually endless streams of vectors which achieve enhanced error coverage only infrequently. Another drawback has been that most error coverage metrics proposed have either been too simplistic or too inefficient to compute. Recently, an effective observability-based statement coverage metric was proposed along with a fast companion procedure for evaluating it. The contribution of our work is the development of a vector generation procedure targeting the observability-based statement coverage metric. Our method uses repeated coverage computation to minimize the number of vectors generated. For vector generation, we propose a novel technique to set up constraints based on the chosen coverage metric. Once the system of interacting arithmetic and Boolean constraints has been set up, it can be solved using hybrid linear programming and Boolean satisfiability methods. We present heuristics to control the size of the constraint system that needs to be solved. We present experimental results which show the viability of automatically generating vectors using our approach for industrial RTL circuits. We envision our system being used during the design process, as well as during post-design debugging.

A methodology for accurate performance evaluation in architecture exploration

Abstract: Presents a system that automatically generates a cycle-accurate and bit-true instruction level simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program running on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hardware implementation model. These figures allow us to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis. In an architecture exploration scheme, both the ILS and the hardware model must be generated automatically, else a substantial programming and hardware design effort has to be expended in each design iteration. Our system uses the ISDL machine description language to support the automatic generation of the ILS and the hardware synthesis model, as well as other related tools.

A text-compression-based method for code size minimization in embedded systems

Abstract: We address the problem of code-size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systemswe use data-compression methods to develop code-size minimization strategies. In our framework, the compressed program consists of a skeleton and a dictionary. We show that the dictionary can be computed by solving a set-covering problem derived from the original program. To execute the compressed code, we describe two methods that have different performance characteristics and different degrees of freedom in compressing the code. We also address performance considerations, and show that they can be incorporated easily into the set-covering formulation, and present experimental results obtained with Texas Instruments' optimizing TMS3220C25 compiler.

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures

Abstract: We address the problem of code generation for DSP systems on a chip. In such systems, the amount of silicon devoted to program ROM is limited, so in addition to meeting various high-performance constraints, the application software must be sufficiently dense. Unfortunately, existing compiler technology is unable to generate high-quality code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. Thus, designers often resort to programming application software in assembly, which is a very tedious and time-consuming task. In this paper, we focus on providing compiler support for a group of specialized architectural features that exist in many DSPs, namely indirect addressing modes with auto-increment/decrement arithmetic. In these DSPs, an indexed addressing mode is generally not available, so automatic variables must be accessed by allocating address registers and performing address arithmetic. Subsuming address arithmetic into auto-increment /decrement arithmetic improves both the performance and size of the generated code. Our objective is to provide a method for comprehensively analyzing the performance benefits and hardware cost due to an auto-increment /decrement feature that varies from-l to +l, and allowing access to k address registers in an address generator. We provide this method via a parameterizable optimization algorithm that operates on a procedure-wise basis. Thus, the optimization techniques in a compiler can be used not only to generate efficient or compact code, but also to help the designer of a custom DSP architecture make decisions on address arithmetic features.

Aviv: a retargetable code generator for embedded processors

Abstract: Embedded systems are broadly defined as systems designed for a particular application. The functionality of an embedded system is divided into hardware and software components. Synthesis of the hardware component involves designing a custom circuit for the hardware portion of the input application. Synthesis of the software component consists of designing a processor that is suited for the software portion of the input application and generating code that implements the functionality of the software component on the designed processor. Short design cycles and increasing embedded system complexity make it impractical to perform manual processor architecture exploration and code generation. In order to effectively explore the design space for the software component of embedded systems, a retargetable code generator is required. This thesis presents the Aviv retargetable code generator that generates optimized machine code for a specified target processor. Aviv is capable of compiling application code into machine code for a variety of architectures. In particular, it is focused on generating code for architectures with instruction-level parallelism. The key problems in code generation are instruction selection, resource allocation, and scheduling. Most current code generation systems solve these problems sequentially. However, these problems are interdependent; therefore, solving them independently can lead to suboptimal code. In order to address the interdependencies, Aviv solves all three problems concurrently. Aviv uses a new graphical representation, the Split-Node DAG, to specify all possible ways of implementing the software component of the application on the target processor. A heuristic algorithm utilizes the information embedded in the Split-Node DAG to solve the various problems of code generation concurrently, thereby identifying a globally optimized solution. Thesis Supervisor: Srinivas Devadas Title: Professor of Electrical Engineering and Computer Science

Coverage-directed validation of hardware models

Abstract: With the rapid increase in the number of transistors that can be fabricated on a single chip, digital systems have become very complex. The increase in the complexity of the digital systems, and the desire to achieve faster time-to-market has made the use of the Computer-Aided Design (CAD) tools indispensable. Designers typically start with writing behavioral or Register-Transfer level (RTL) description of the system functionality using a hardware Description Language (HDL). After that they transform the HDL description to the gate-level, transistor level, and finally generate mask-level layout which is used to manufacture the chip. CAD tools are used extensively to execute transformations between different levels of abstraction. They also help to optimize the design so as to achieve better performance and meet different constraints relating to speed, power consumption, and area. In order to have a working chip, the designer has to make sure that the original HDL description is correct and also that no error is introduced during transformations to the lower levels. Currently validation of the initial HDL description and verifying the design in different levels of abstraction against each other is a major bottleneck in the design process. Because the HDL description is usually the first description of the design, simulation is the primary methodology for validating it. Simulation-based verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Simulation-based validation has suffered from a disconnect between the metrics used to measure the coverage of a set of simulation vectors and the vector generation process. This disconnect has resulted in the simulation of virtually endless streams of vectors which achieve enhanced coverage only infrequently. Another drawback has been that most coverage metrics proposed have either been too simplistic or too inefficient to compute. This thesis provides the details of an efficient method to compute an Observability-based Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs. It also introduces a new method for generating test vectors under any coverage metric. In this thesis the problem of generating test vectors for both combinational and sequential circuits under OCCOM is discussed. A prototype system which generates test vectors under the OCCOM coverage metric has been built. The system can be used during the design process, as well as during post-design debugging to validate the initial HDL description. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

A probabilistic approach for RT-level power modeling

Abstract: We propose a method for register-transfer level (RTL) power modeling. The switched capacitance and switching probability of each output of a functional module are modeled by formulas that are a function of the module's inputs probabilities. These formulas are computed beforehand for each module using the polynomial simulation scheme, and stored in the module library. The switched capacitance (and thus power) for each instance of a module in the circuit can then be efficiently evaluated for its specific input probabilities. The switching probabilities at the outputs of each module can be computed in a similar manner, thus providing a means of propagating the switching probabilities through the circuit described at the RT level. We provide a set of experimental results that show that this method provides estimates close to the logic-level estimates, but is orders of magnitude faster.

Automatic architecture evaluation for hardware/software codesign

Abstract: Hardware/software codesign requires an accurate way of evaluating candidate architectures. Architecture exploration (which can be used to automate hardware/software codesign) requires an automatic way of evaluating candidate architectures, otherwise a substantial programming effort must be expended on each iteration. We present a system that automatically generates an instruction level simulator (ILS) and a hardware implementation model given a description of a candidate architecture. Accurate cycle counts can be obtained for specific applications using the ILS. At the same time, the hardware implementation model can be used to obtain cycle length, die size, and power consumption estimates. These measurements allow an accurate performance evaluation to be constructed for each candidate architecture. We use the machine description language ISDL to support the generation of the ILS and the hardware model, as well as other tools which form the core of our hardware/software codesign system.

The MASC Composable Computing Infrastructure for intelligent environments

Abstract: Presents a system architecture and framework for creating rapidly deployable intelligent environments. The rapid pace of innovation of computer hardware and intelligent systems software has led to uncertainty that is deterring manufacturers from adopting a single processor, network or software environment for placement into their products. The MASC Composable Computing Infrastructure addresses these issues by providing an upgradable hardware and software infrastructure that supports rapid development and deployment, as well as simple and economical maintenance of intelligent environment systems.