Showing papers by "Srinivas Devadas published in 2000"

Application-specific memory management for embedded systems using software-controlled caches

Abstract: We propose a way to improve the performance of embedded processors running data-intensive applications by allowing software to allocate on-chip memory on an application-specific basis. On-chip memory in the form of cache can be made to act like scratch-pad memory via a novel hardware mechanism, which we call column caching. Column caching enables dynamic cache partitioning in software, by mapping data regions to a specified sets of cache “columns” or “ways.” When a region of memory is exclusively mapped to an equivalent sized partition of cache, column caching provides the same functionality and predictability as a dedicated scratchpad memory for time-critical parts of a real-time application. The ratio between scratchpad size and cache size can be easily and quickly varied for each application, or each task within an application. Thus, software has much finer software control of on-chip memory, providing the ability to dynamically tradeoff performance for on-chip memory.

Observability analysis of embedded software for coverage-directed validation

Abstract: The most common approach to checking correctness of a hardware or software design is to verify that a description of the design has the proper behavior as elicited by a series of input stimuli. In the case of software, the program is simply run with the appropriate inputs, and in the case of hardware, its description written in a hardware description language (HDL) is simulated with the appropriate input vectors. In coverage-directed validation, coverage metrics are defined that quantitatively measure the degree of verification coverage of the design. Motivated by recent work on observability-based coverage metrics for models described in a hardware description language, we develop a method that computes an observability-based code coverage metric for embedded software written in a high-level programming language. Given a set of input vectors, our metric indicates the instructions that had no effect on the output. An assignment that was not relevant to generate the output value cannot be considered as being covered. Results show that our method offers a significantly more accurate assessment of design verification coverage than statement coverage. Existing coverage methods for hardware can be used with our method to build a verification methodology for mixed hardware/software or embedded systems.

Solving covering problems using LPR-based lower bounds

Abstract: Unate and binate covering problems are a subclass of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization and technology mapping, are formulated. Previous branch-and-bound methods for solving these problems exactly use lower bounding techniques based on finding maximal independent sets. In this paper, we examine lower bounding techniques based on linear programming relaxation (LPR) for the covering problem. We show that a combination of traditional reductions (essentiality and dominance) and incremental computation of LPR-based lower bounds can exactly solve difficult covering problems orders of magnitude faster than traditional methods.

ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration

Abstract: Wepresent the Instruction Set Description Language, ISDL, a machinedescription language used to describe target architectures toa set of retargetable design tools including compilers and simulators.Such tools enable the design of embedded system processors bysupporting the exploration of the architecture design space.The features and flexibility of ISDL enable the description ofa wide variety of architectures with emphasis on VLIW architectures.ISDL explicitly supports constraints that define valid operationgroupings within an instruction, thus increasing the range ofspecifiable architectures and resulting in concise and intuitivedescriptions. Furthermore, a single ISDL description supportsthe automatic generation or retargeting of all of the designevaluation tools. This paper presents the structure and featuresof ISDL and describes how the information in an ISDL descriptionmay be used to retarget or generate assemblers, disassemblers,compilers, simulators, and hardware models. In addition, it comparesISDL to various other machine description languages that arebeing used for embedded processor design. Various complicationsthat arose while describing real-world architectures (which includea powerful seven-way VLIW processor and the Motorola 56000 DSP)and the solutions to these complications are also presented.

VLSI: Systems on a Chip

Abstract: A downconversion mixer for wideband CDMA application is designed and fabricated in a 0.5 p.m CMOS technology. The mixer operates at 2.4 GHz frequency with a 3 V power supply and consumes only 4.5 mW power. Targeting in designing high performance mixers of high yield within short design cyde, this paper addresses RF mixer design issues from an optimization and statistical point of view, and derived the noise equation based on a simple noise model of the Gilbert-cell mixer. The mixer achieved a conversion gain of 14.3 dB, a SSB noise figure of 10.4 dB, and an IIP3 of -8 dBm.

A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design

Abstract: We present a new approach for solving the hardware-software partitioning problem in embedded system design. Our approach is based on transforming an instance of the hardware-software partitioning problem into an instance of a deterministic scheduling with rejection problem that minimizes a function of the completion times of the tasks. A solution to this real-time scheduling problem yields a partition of the system functionality and provides valuable feedback to the system designer. Experimental results indicate that the simplicity and effective solution techniques of our approach make it ideally suited as an automated design analysis tool in embedded system design.

Scheduling for hardware-software partitioning in embedded system design

Abstract: I present a new approach that solves the hardware-software partitioning problem for small embedded systems. Small application specific digital systems, often referred to as embedded systems, are often implemented using both hardware and software. Due to the impact that the hardware-software partition of the system functionality has on the system performance and cost, determining an optimal or near optimal hardware-software partition is essential to building a system that meets its performance criteria at minimal cost. My approach to solving the hardware-software partitioning problem is based on transforming an instance of the partitioning problem into an instance of a deterministic scheduling with rejection problem that minimizes a function of the completion times of the tasks. Although this scheduling problem is strongly NP -hard, it has been studied extensively, and several effective solution techniques are available. I leverage these techniques to develop an efficient and effective hardware-software partitioning scheme for small embedded systems. In addition to the new partitioning scheme, I present new complexity bounds for several variants of the scheduling problem. These complexity bounds illustrate the usefulness and futility of modifying the system characteristics to obtain a more easily solved scheduling problem formulation. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

An architecture synthesis system for embedded processors

Abstract: Design requirements for embedded systems call for architectures with small size, low power consumption and low cost. These requirements can be met by designing custom architectures for every single application. However, the commercial viability of embedded systems calls for short design cycles. These requirements are conflicting: custom architectures take a long time and substantial effort to produce, because of the need to manually generate design evaluation tools, such as simulators and compilers, for each architecture candidate. This conflict can be eliminated by providing a system capable of generating all design evaluation tools for a given candidate architecture. This thesis presents two components of the ARIES environment for architecture synthesis: the machine description language ISDL and the G ENSIM simulator generator system. We also briefly describe the H GEN hardware model generator. In the ARIES system, candidate architectures are described in the ISDL language. From this machine description, component tools can automatically generate design evaluation tools, namely an assembler, Instruction Level Simulator, and disassembler. These tools can be used to evaluate each candidate architecture and make improvements. The whole process can be used to implement an architecture exploration loop which provides the benefits of custom architectures while maintaining short design cycles. Preliminary results also show that it is possible to generate retargetable compilers and hardware models from the same machine description. ISDL is a flexible machine description language that supports a wide range of architectures and features with special emphasis on VLIW architectures. It provides sufficient information to generate all the tools from a single machine description, and provides constraints which make the machine descriptions concise and intuitive. The GENSIM simulator generator is a tool that can automatically produce fast (4.5 Mops, cycle-accurate, bit-true Instruction Level Simulators from ISDL descriptions in a short time. We present experimental results which show that I SDL is flexible enough to describe a wide range of architectures implementing a broad range of architectural features. We also present experimental results demonstrating the capabilities of the GENSIM system and the generated simulators. Finally we present results that demonstrate the feasibility of architecture exploration based on automatically generated design evaluation tools. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)