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Srinivas Devadas

Researcher at Massachusetts Institute of Technology

Publications -  498
Citations -  35003

Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.

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Patent

Reliable puf value generation by pattern matching

TL;DR: In this article, a method was proposed to reliably provision and re-generate a finite and exact sequence of bits for use with cryptographic applications, e.g., as a key, by employing one or more challengeable PUF circuit elements.
Patent

Securely field configurable device

TL;DR: In this article, a secure field configurable device (FPGA) supports secure field configuration without using nonvolatile storage for cryptographic keys on the device and without requiring a continuous or ongoing power source to maintain a volatile storage.
Proceedings ArticleDOI

CraterLake: a hardware accelerator for efficient unbounded computation on encrypted data

TL;DR: This work presents CraterLake, the first FHE accelerator that enables FHE programs of unbounded size (i.e., unbounded multiplicative depth), and introduces a new hardware architecture that efficiently scales to very large cipher-texts, novel functional units to accelerate key kernels, and new algorithms and compiler techniques to reduce data movement.
Book ChapterDOI

The Trusted Execution Module: Commodity General-Purpose Trusted Computing

TL;DR: The Trusted Execution Module is introduced; a high-level specification for a commodity chip that can execute user-supplied procedures in a trusted environment and its guarantees of secure execution enable exciting applications that include mobile agents, peer-to-peer multiplayer online games, and anonymous offline payments.
Journal ArticleDOI

A unified approach to the synthesis of fully testable sequential machines

TL;DR: An attempt is made to unify and extend the various approaches to synthesizing fully testable sequential circuits that can be modeled as finite state machines (FSMs) by identifying classes of redundancies and isolating equivalent-state redundancies as those most difficult to eliminate.