Srinivas Devadas

Bio: Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.

Redundancies and don't cares in sequential logic synthesis

Abstract: The authors explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty state transition graph (STG) that is equivalent to the STG of the true machine. The authors present a classification of redundant faults in sequential circuits composed of single or interacting finite-state machines. Don't care sets can be defined for each class of redundancy, and optimally exploiting these don't care conditions results in the implicit elimination of any such redundancies in a given circuit. In cascaded and interconnected sequential circuits, sequential don't cares are required to eliminate redundancies. The authors present preliminary experimental results which indicate that by exploiting these don't cares medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times. >

Sequential test generation at the register-transfer and logic levels

Abstract: The problem of test generation for non-scan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. Our approach is targeted at chips with data-path like STG.The problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. Standard combinational test generation algorithms are used to generate test vectors for stuck-at faults in the logic-level implementation. The required state corresponding to the test vector is justified using a fault-free justification step that is performed using the RTL specification. Similarly, if the effect of the fault has been propagated by the test vector to the flip-flop inputs alone, the faulty state produced is differentiated from the true next state by a differentiation step that uses the RTL specification.New and efficient algorithms for fault-free state justification and differentiation on RTL descriptions that contain arithmetic as well as random logic modules are described. Unlike previous approaches, this approach does not require the storage of covers or a partial STG and can be used to generate tests for entire chips without scan. Exploiting RTL information, together with a new conflict resolution technique results in improvements of up to 100X in performance over sequential test generation techniques restricted to operate at the logic level. We have successfully generated tests for the viterbi speech processor chip [18].

On The Verification of Sequential Machines at Differing Levels of Abstraction

Abstract: In this paper, an algorithm is presented for the verification of the equivalence of two sequential circuit descriptions at the same or differing levels of abstraction, namely at the register-transfer (RT) level and the logic level. The descriptions represent general finite automata at the differing levels -- a finite automaton can be described in a ISP-like language and its equivalence to a logic level implementation can be verified using our algorithm. Two logic level automatons can be similarly verified for equivalence. Previous approaches to sequential circuit verification have been restricted to verifying relatively simple descriptions with small amounts of memory. Unlike these approaches, our technique is shown to be computationally efficient for much more complex circuits. The efficiency of our algorithm lies in the exploitation of don't care information derivable from the RTL or logic level description (e.g invalid input and output sequences) during the verification process. Using efficient cube enumeration procedures at the logic level we have been able to verify the equivalence of finite automata with a large number of states in small amounts of cpu-time.

Optimal logic synthesis and testability: two faces of the same coin

Abstract: The relationships between test generation and logic minimization are described. An overview of the state of the art in combinational and sequential logic synthesis is provided. Combinational logic synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination logic can be obtained as a by-product of the logic minimization step. Equally intimate relationships between the problems of sequential logic synthesis and sequential test generation are envisioned. A recently developed synthesis technique of constrained state assignment and logic optimization which ensures fully testable sequential machines is described briefly. >

Comparing two-level and ordered binary decision diagram representations of logic functions

Abstract: An example is given of a class of functions with 2n+logn inputs that have two-level or sum-of-products representations containing n/sup 2/ product terms and ordered binary decision diagram representations that have at least Omega (1/sup n/2/) vertices under any possible variable ordering. >

TaintDroid: An Information-Flow Tracking System for Realtime Privacy Monitoring on Smartphones

Abstract: Today’s smartphone operating systems frequently fail to provide users with visibility into how third-party applications collect and share their private data. We address these shortcomings with TaintDroid, an efficient, system-wide dynamic taint tracking and analysis system capable of simultaneously tracking multiple sources of sensitive data. TaintDroid enables realtime analysis by leveraging Android’s virtualized execution environment. TaintDroid incurs only 32p performance overhead on a CPU-bound microbenchmark and imposes negligible overhead on interactive third-party applications. Using TaintDroid to monitor the behavior of 30 popular third-party Android applications, in our 2010 study we found 20 applications potentially misused users’ private information; so did a similar fraction of the tested applications in our 2012 study. Monitoring the flow of privacy-sensitive data with TaintDroid provides valuable input for smartphone users and security service firms seeking to identify misbehaving applications.

TaintDroid: an information-flow tracking system for realtime privacy monitoring on smartphones

Abstract: Today's smartphone operating systems frequently fail to provide users with adequate control over and visibility into how third-party applications use their private data. We address these shortcomings with TaintDroid, an efficient, system-wide dynamic taint tracking and analysis system capable of simultaneously tracking multiple sources of sensitive data. TaintDroid provides realtime analysis by leveraging Android's virtualized execution environment. TaintDroid incurs only 14% performance overhead on a CPU-bound micro-benchmark and imposes negligible overhead on interactive third-party applications. Using TaintDroid to monitor the behavior of 30 popular third-party Android applications, we found 68 instances of potential misuse of users' private information across 20 applications. Monitoring sensitive data with TaintDroid provides informed use of third-party applications for phone users and valuable input for smartphone security service firms seeking to identify misbehaving applications.

Symbolic Boolean manipulation with ordered binary-decision diagrams

Abstract: Ordered Binary-Decision Diagrams (OBDDs) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satisfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD data structures. Using OBDDs, a wide variety of problems can be solved through symbolic analysis. First, the possible variations in system parameters and operating conditions are encoded with Boolean variables. Then the system is evaluated for all variations by a sequence of OBDD operations. Researchers have thus solved a number of problems in digital-system design, finite-state system analysis, artificial intelligence, and mathematical logic. This paper describes the OBDD data structure and surveys a number of applications that have been solved by OBDD-based symbolic analysis.

Physical unclonable functions for device authentication and secret key generation

Abstract: Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.