S
Srinivas Devadas
Researcher at Massachusetts Institute of Technology
Publications - 498
Citations - 35003
Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.
Papers
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Journal ArticleDOI
Aegis: A Single-Chip Secure Processor
TL;DR: A single-chip secure processor called Aegis incorporates mechanisms to protect the integrity and privacy of applications from physical attacks as well as software attacks, and physically secure systems can be built using this processor.
Journal ArticleDOI
Test generation for sequential circuits
TL;DR: The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits.
Proceedings ArticleDOI
Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching
TL;DR: Slender PUF protocol is lightweight and does not require costly additional error correction, fuzzy extractors, and hash modules suggested in most previously known PUF-based robust authentication techniques, and has the great advantage of an inbuilt PUF error tolerance.
Proceedings ArticleDOI
A secure processor architecture for encrypted computation on untrusted programs
TL;DR: A secure processor architecture is proposed, called Ascend, that guarantees privacy of data when arbitrary programs use the data running in a cloud-like environment and does not disclose what instruction is being run at any given time.
Patent
Authentication of integrated circuits
TL;DR: In this paper, a group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each devices having a measurement module for measuring the measurable characteristics.