S
Srinivas Devadas
Researcher at Massachusetts Institute of Technology
Publications - 498
Citations - 35003
Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.
Papers
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Proceedings ArticleDOI
Recent progress in synthesis for testability
TL;DR: Initial results at combining synthesis for testability approaches with register-transfer level automatic test-pattern generation to produce vector sets that give complete single stuck-at fault coverage without the use of scan.
Scalable directoryless shared memory coherence using execution migration
TL;DR: This work argues that with EM scaling performance has much lower cost and design complexity than in directorybased coherence and traditional NUCA architectures: by merely scaling network bandwidth from 128 to 256 (512) bit flits, the performance of the architecture improves by an additional 8% (12%), while the baselines show negligible improvement.
Posted Content
Sanctum: Minimal RISC Extensions for Isolated Execution.
TL;DR: Sanctum as mentioned in this paper is a set of minimal extensions to a standard RISC architecture that offers strong provable isolation of software modules running concurrently and sharing resources, which is similar to SGX in its API, but protects against an important class of additional software attacks.
A computer-aided design methodology for low power sequential logic circuits
José Monteiro,Srinivas Devadas +1 more
TL;DR: A methodology for low power design based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle is developed.
Proceedings ArticleDOI
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
Srinivas Devadas,Kurt Keutzer +1 more
TL;DR: The tasks of synthesizing the BIST logic and directed test pattern generation (DTPG) are intertwined to maximize the resulting fault coverage and this approach is applicable to a variety of BIST strategies including those that use linear- and nonlinear-feedback shift registers.