Today’s smartphone operating systems frequently fail to provide users with visibility into how third-party applications collect and share their private data. We address these shortcomings with TaintDroid, an efficient, system-wide dynamic taint tracking and analysis system capable of simultaneously tracking multiple sources of sensitive data. TaintDroid enables realtime analysis by leveraging Android’s virtualized execution environment. TaintDroid incurs only 32p performance overhead on a CPU-bound microbenchmark and imposes negligible overhead on interactive third-party applications. Using TaintDroid to monitor the behavior of 30 popular third-party Android applications, in our 2010 study we found 20 applications potentially misused users’ private information; so did a similar fraction of the tested applications in our 2012 study. Monitoring the flow of privacy-sensitive data with TaintDroid provides valuable input for smartphone users and security service firms seeking to identify misbehaving applications.

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TaintDroid: An Information-Flow Tracking System for Realtime Privacy Monitoring on Smartphones

Today's smartphone operating systems frequently fail to provide users with adequate control over and visibility into how third-party applications use their private data. We address these shortcomings with TaintDroid, an efficient, system-wide dynamic taint tracking and analysis system capable of simultaneously tracking multiple sources of sensitive data. TaintDroid provides realtime analysis by leveraging Android's virtualized execution environment. TaintDroid incurs only 14% performance overhead on a CPU-bound micro-benchmark and imposes negligible overhead on interactive third-party applications. Using TaintDroid to monitor the behavior of 30 popular third-party Android applications, we found 68 instances of potential misuse of users' private information across 20 applications. Monitoring sensitive data with TaintDroid provides informed use of third-party applications for phone users and valuable input for smartphone security service firms seeking to identify misbehaving applications.

/pdf/taintdroid-an-information-flow-tracking-system-for-realtime-3fnz9lwdso.pdf

TaintDroid: an information-flow tracking system for realtime privacy monitoring on smartphones

Ordered Binary-Decision Diagrams (OBDDs) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satisfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD data structures. Using OBDDs, a wide variety of problems can be solved through symbolic analysis. First, the possible variations in system parameters and operating conditions are encoded with Boolean variables. Then the system is evaluated for all variations by a sequence of OBDD operations. Researchers have thus solved a number of problems in digital-system design, finite-state system analysis, artificial intelligence, and mathematical logic. This paper describes the OBDD data structure and surveys a number of applications that have been solved by OBDD-based symbolic analysis.

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Symbolic Boolean manipulation with ordered binary-decision diagrams

Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.

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Physical unclonable functions for device authentication and secret key generation

Physical Unclonable Functions for Device Authentication and Secret Key Generation

The increasing complexity of embedded systems is accelerating the use of multicore processors in these systems. This trend gives rise to new problems such as the sharing of on-chip network resources among hard real-time and normal best effort data traffic. We propose a network-on-chip router that provides predictable and deterministic communication latency for hard real-time data traffic while maintaining high concurrency and throughput for best-effort/general-purpose traffic with minimal hardware overhead. The proposed router requires less area than non-interfering networks, and provides better Quality of Service (QoS) in terms of predictability and determinism to hard real-time traffic than priority-based routers. We present a deadlock-free algorithm for decoupled routing of the two types of traffic. We compare the area and power estimates of three different router architectures with various QoS schemes using the IBM 45-nm SOI CMOS technology cell library. Performance evaluations are done using three realistic benchmark applications: a hybrid electric vehicle application, a utility grid connected photovoltaic converter system, and a variable speed induction motor drive application.

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Low-overhead hard real-time aware interconnect network router

Design requirements for embedded systems call for architectures with small size, low power consumption and low cost. These requirements can be met by designing custom architectures for every single application. However, the commercial viability of embedded systems calls for short design cycles. These requirements are conflicting: custom architectures take a long time and substantial effort to produce, because of the need to manually generate design evaluation tools, such as simulators and compilers, for each architecture candidate. This conflict can be eliminated by providing a system capable of generating all design evaluation tools for a given candidate architecture. 
This thesis presents two components of the ARIES environment for architecture synthesis: the machine description language ISDL and the G ENSIM simulator generator system. We also briefly describe the H GEN hardware model generator. In the ARIES system, candidate architectures are described in the ISDL language. From this machine description, component tools can automatically generate design evaluation tools, namely an assembler, Instruction Level Simulator, and disassembler. These tools can be used to evaluate each candidate architecture and make improvements. The whole process can be used to implement an architecture exploration loop which provides the benefits of custom architectures while maintaining short design cycles. Preliminary results also show that it is possible to generate retargetable compilers and hardware models from the same machine description. 
ISDL is a flexible machine description language that supports a wide range of architectures and features with special emphasis on VLIW architectures. It provides sufficient information to generate all the tools from a single machine description, and provides constraints which make the machine descriptions concise and intuitive. The GENSIM simulator generator is a tool that can automatically produce fast (4.5 Mops, cycle-accurate, bit-true Instruction Level Simulators from ISDL descriptions in a short time. We present experimental results which show that I SDL is flexible enough to describe a wide range of architectures implementing a broad range of architectural features. We also present experimental results demonstrating the capabilities of the GENSIM system and the generated simulators. Finally we present results that demonstrate the feasibility of architecture exploration based on automatically generated design evaluation tools. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

An architecture synthesis system for embedded processors

A theoretical framework for the minimization of logic functions with symbolic or multiple-valued outputs is presented. By use of this framework, efficient, exact algorithms for the problems of output encoding and finite-state-machine (FSM) state assignment are developed. All previous automatic approaches to these encoding problems have involved the use of heuristic techniques. A notion of generalized prime implicants is presented for functions with multiple-valued outputs, and a novel minimization procedure of prime implicant generation and covering for solving the output encoding problem is proposed. An optimum solution to this covering problem is also an optimum solution to the encoding problem. A single logic minimization step thus replaces on the order of n-factorial minimizations required by straightforward exhaustive search. It has been shown previously that the input encoding problem can be exactly solved using Boolean minimization over functions with multiple-valued inputs. An extension of the presented algorithm that handles functions with multiple-valued inputs and outputs can be used to solve the state assignment problem exactly. Experimental results are presented for a set of examples. >

Minimization of functions with multiple-valued outputs: theory and applications

Our ability to characterize protein structure and dynamics is vastly outpaced by the speed of modern genetic sequencing, creating a growing divide between our knowledge of biological sequence and structure. Structural modeling algorithms offer the hope to bridge this gap through computational exploration of the sequence determinants of structure diversity. 
In this thesis, we introduce new algorithms that enable the efficient modeling of protein structure ensembles and their sequence variants. These statistical mechanics-based constructions enable the identification of all energetically likely sequence/structure states for a family of proteins. Beyond improved structure predictions, this approach enables a framework for thermodynamically-driven mutational and comparative analysis as well as the approximation of kinetic protein folding pathways. 
We have applied these techniques to two protein types that are notoriously difficult to characterize biochemically: transmembrane β-barrel proteins and amyloid fibrils. For these we advance the state-of-the-art in structure prediction, mutational analysis, and sequence alignment. Further, we have collaborated to apply these methods to open scientific questions about amyloid fibrils and bacterial biofilms. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Ensemble modeling of beta-sheet proteins

In this paper, we consider the problem of designing Differentially Private (DP) algorithms for Stochastic Convex Optimization (SCO) on heavy-tailed data. The irregularity of such data violates some key assumptions used in almost all existing DP-SCO and DP-ERM methods, resulting in failure to provide the DP guarantees. To better understand this type of challenges, we provide in this paper a comprehensive study of DP-SCO under various settings. First, we consider the case where the loss function is strongly convex and smooth. For this case, we propose a method based on the sample-and-aggregate framework, which has an excess population risk of $\tilde{O}(\frac{d^3}{n\epsilon^4})$ (after omitting other factors), where $n$ is the sample size and $d$ is the dimensionality of the data. Then, we show that with some additional assumptions on the loss functions, it is possible to reduce the \textit{expected} excess population risk to $\tilde{O}(\frac{ d^2}{ n\epsilon^2 })$. To lift these additional conditions, we also provide a gradient smoothing and trimming based scheme to achieve excess population risks of $\tilde{O}(\frac{ d^2}{n\epsilon^2})$ and $\tilde{O}(\frac{d^\frac{2}{3}}{(n\epsilon^2)^\frac{1}{3}})$ for strongly convex and general convex loss functions, respectively, \textit{with high probability}. Experiments suggest that our algorithms can effectively deal with the challenges caused by data irregularity.

Srinivas Devadas

Papers

Low-overhead hard real-time aware interconnect network router

An architecture synthesis system for embedded processors

Minimization of functions with multiple-valued outputs: theory and applications

Ensemble modeling of beta-sheet proteins

On Differentially Private Stochastic Convex Optimization with Heavy-tailed Data