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Srinivas Devadas

Researcher at Massachusetts Institute of Technology

Publications -  498
Citations -  35003

Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.

Papers
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Journal ArticleDOI

Simultaneous Alignment and Folding of Protein Sequences

TL;DR: PartiFold-Align as discussed by the authors exploits sparsity in the set of super-secondary structure pairings and alignment candidates to achieve an effectively cubic running time for simultaneous pairwise alignment and folding.
Proceedings ArticleDOI

Trellis: Robust and Scalable Metadata-private Anonymous Broadcast

TL;DR: Trellis as discussed by the authors is a mix-net based anonymous broadcast system with cryptographic security guarantees, which hides all network-level metadata, remains robust to changing network conditions, guarantees availability to honest users, and scales with the number of mix servers.
Proceedings ArticleDOI

Testability driven synthesis of interacting finite state machines

TL;DR: It is shown that the sequential testability of an FSM can be enhanced more easily when the machine is recognized to be, or is synthesized as, an interconnection of smaller machines.
Posted Content

Constants Count: Practical Improvements to Oblivious RAM

TL;DR: Ring ORAM as discussed by the authors is the first tree-based ORAM whose bandwidth is independent of the ORAM bucket size, a property that unlocks multiple performance improvements, such as 2.3× to 4× better than Path ORAM, the prior-art scheme for small client storage.
Book ChapterDOI

Optimization Techniques for Low Power Circuits

TL;DR: Now that tools which can efficiently estimate the average power dissipation of combinational and sequential logic circuits are developed, there is a means of comparing different implementations of the same system, and therefore a way to direct logic synthesis tools for low power optimization.