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Srinivas Devadas

Researcher at Massachusetts Institute of Technology

Publications -  498
Citations -  35003

Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.

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A Low-Latency, Low-Area Hardware Oblivious RAM Controller

TL;DR: Tiny ORAM as discussed by the authors is the first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes) and can finish an access in 1.4μs, over 40× faster than the prior-art implementation.

A Low-Latency, Low-Area Hardware Oblivious RAM Controller

TL;DR: Tiny ORAM as discussed by the authors is the first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes), with a 64 Byte block size, over 40x faster than the prior-art implementation.
Posted Content

Taurus: Lightweight Parallel Logging for In-Memory Database Management Systems (Extended Version).

TL;DR: Taurus as mentioned in this paper tracks and encodes transaction dependencies using a vector of log sequence numbers (LSNs), which ensure that the dependencies are fully captured in logging and correctly enforced in recovery.