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Srinivasa Konala

Bio: Srinivasa Konala is an academic researcher from University of Kentucky. The author has contributed to research in topics: Programmable logic device & Field-programmable gate array. The author has an hindex of 6, co-authored 6 publications receiving 397 citations.

Papers
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Proceedings ArticleDOI
28 Apr 1996
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, achieving BIST without any area overhead or performance penalties to the system function implemented by the FPGA.
Abstract: We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.

167 citations

Proceedings ArticleDOI
15 Feb 1996
TL;DR: A new approach for FPGA testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, without area or performance penalties to the system function implemented by the FPGa.
Abstract: We present a new approach for FPGA testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without area or performance penalties to the system function implemented by the FPGA, since the FPGA is reconfigured for normal system operation. An analysis of Look-Up Table (LUT) based FGPA architectures yields a general expression for the number of test sessions and establishes the bounds on FPGA logic resources required to minimize the number of BIST configurations required to completely test all of the programmable logic blocks of an FPGA.

81 citations

Proceedings ArticleDOI
20 Oct 1996
TL;DR: In this paper, an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays.
Abstract: We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.

72 citations

01 Jan 2000
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, and is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed.
Abstract: We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcolme these limitations.’

50 citations

01 Jan 1996
TL;DR: A new approach for Field Programma- ble Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, without any area overhead or performance penalties to the system function implemented by the FPGA.
Abstract: We present a new approach for Field Programma- ble Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maxi- mal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programma- ble logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcolme these limitations. '

20 citations


Cited by
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Patent
18 Nov 1998
TL;DR: In this paper, an electronic design automation (EDA) software tool running on a computer system allows signals to be captured both before and after a trigger condition (breakpoint) in a programmable logic device.
Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

244 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: The first BIST approach for testing the programmable routing network in FPGAs is introduced, which detects opens in, and shorts among, wiring segments, and also faults affecting theprogrammable switches that configure the FPGA interconnect.
Abstract: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

180 citations

Patent
Alan L. Herrmann1, P Nujent Gregg1
27 Oct 1997
TL;DR: In this article, the authors propose a technique for embedding a logic analyzer in a programmable logic device (PLD), which allows debugging of such a device in its actual operating conditions.
Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigger condition may be changed without recompiling. The design may be recompiled with new logic analyzer parameters to debug a different portion.

172 citations

Journal ArticleDOI
TL;DR: A new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) to provide redundant backup for several types of components.
Abstract: Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) The physical design is partitioned into a set of tiles In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead

171 citations

Journal ArticleDOI
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

170 citations