Srinivasa Rao Pathapati

Bio: Srinivasa Rao Pathapati is an academic researcher. The author has contributed to research in topics: Effective number of bits & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 1 citations.

All-Digital ADC Design in 65 nm CMOS Technology

Abstract: The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital dom ...

Design of an all-digital, reconfigurable sigma-deltamodulator

Abstract: This thesis presents a model of reconfigurable sigma-delta modulator. These modulators areintended for high speed digital Digital to Analog Converters. The modulators are intendedto reduce complexity of current steering DACs and also considered as a front end of dataconverters. Quantization noise present in digital signal is pushed to higher frequencies bysigma-delta modulators. Noise in high band frequencies can be removed by a low pass filter.A test methodology involving generation of baseband signal, interpolation and digitizationis opted. Topologies tested in MATLAB® include signal feedback and error feedback modelsof first-order and second-order sigma-delta modulators. Error feedback and signal feedbackfirst-order modulators’ performance is quite similar. The SNR of a first-order error feedbackmodel is 52.3 dB and 55.9 dB for 1 and 2 quantization bits, respectively. In second-orderSDM, signal feedback provides best performance with 80 dB SNR.The other part of the thesis focuses on the implementation of the sigma-delta modulator(SDM) using faster time to market approach. SoC Encounter, a tool from Cadence, is theeasiest way to do this job. The modulators are implemented in 65-nm technology. The reconfigurablesigma-delta modulator is designed using Verilog-HDL language. Switches areintroduced to control the reconfigurable SDM for different input word lengths. Word-lengthcan vary from 0 to 4 bits. Modulator is designed to work for frequencies of 2 GHz. To netlistthe design, Design Compiler is used which is a tool from Synopsys®.The area of the chip reported by design compiler is 563.68 um. When the design is implementedin SoC Encounter, area of the chip is increased, because the core utilization, whiledesigning, is only 60%, which is 556.8 um. Remaining 40% area is used by buffers, inverterand filler cells during clock tree synthesis. The buffers and inverters are added to removethe clock phase delay between different registers. Power consumption of the chip is 319mW.Internal power of the modulators is 219.1 mW. Switching power of output capacitances is99.9 mW, which is 31% of the total power consumed. Main concern of the power loss isconsidered to be power leakage. To reduce the leakage power and achieve high speed designCORE65GPHVT libraries are used. Leakage power of the design is 2.825 uW which is0.00088% of the total power.