Srivatsava Jandhyala

Bio: Srivatsava Jandhyala is an academic researcher from International Institute of Information Technology, Hyderabad. The author has contributed to research in topics: Voltage & MOSFET. The author has an hindex of 6, co-authored 24 publications receiving 209 citations. Previous affiliations of Srivatsava Jandhyala include University of California, Berkeley & Information Technology Institute.

BSIM—SPICE Models Enable FinFET and UTB IC Designs

Abstract: Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

BSIM compact MOSFET models for SPICE simulation

Abstract: Continuous technology advancements have forced MOSFET architecture to evolve from bulk to SOI to multigate MOSFETs. BSIM compact models have helped circuit designers to realize their designs first time correct using accurate physical models used in SPICE simulation. BSIM3 and BSIM4 are threshold voltage based bulk MOSFET models while BSIM6 is charge based bulk MOSFET model, which include physical effects such as mobility degradation, current saturation, high frequency models etc. BSIM6 has been developed especially to address symmetry around Vds = 0, thus providing smooth higher order derivatives. BSIM-CMG is a CMC standard surface potential based model for common symmetric double, triple, quadruple and surround gate (nanowire) MOSFETs. Long channel DIBL also called Drain-Induced Threshold Shift (DITS) effect and asymmetric charge weighing factor etc. have been recently included in it. BSIM-IMG is a surface potential based model to simulate ultra-thin body devices such as UTBSOI but also other thin body devices such as MOS2 transistor.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Abstract: Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Abstract: Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.

PrxCa1−xMnO3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem

Abstract: The neural network enables efficient solutions for Nondeterministic Polynomial-time (NP) hard problems, which are challenging for conventional von Neumann computing. The hardware implementation, i.e., neuromorphic computing, aspires to enhance this efficiency by custom hardware. Particularly, NP hard graphical constraint optimization problems are solved by a network of stochastic binary neurons to form a Boltzmann Machine (BM). The implementation of stochastic neurons in hardware is a major challenge. In this work, we demonstrate that the high to low resistance switching (set) process of a PrxCa1−xMnO3 (PCMO) based RRAM (Resistive Random Access Memory) is probabilistic. Additionally, the voltage-dependent probability distribution approximates a sigmoid function with 1.35%–3.5% error. Such a sigmoid function is required for a BM. Thus, the Analog Approximate Sigmoid (AAS) stochastic neuron is proposed to solve the maximum cut—an NP hard problem. It is compared with Digital Precision-controlled Sigmoid (DPS) implementation using (a) pure CMOS design and (b) hybrid (RRAM integrated with CMOS). The AAS design solves the problem with 98% accuracy, which is comparable with the DPS design but with 10× area and 4× energy advantage. Thus, ASIC neuro-processors based on novel analog neuromorphic devices based BM are promising for efficiently solving large scale NP hard optimization problems.

Design Of Analog Cmos Integrated Circuits

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Design Of Analog Cmos Integrated Circuits

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FinFETs: From Devices to Architectures

Abstract: Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Abstract: We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.